EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 243
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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ParllIfIn
DS785UM1
31
15
Address: 0x8003_005C
Default: 0x0000_0000
Definition: Parallel Interface Output/Control Register
Bit Descriptions:
30
14
29
13
28
12
This register, if PIFEN = ‘1’ in the
Smart Panel. A Smart Panel has an integrated controller and frame buffer.
RSVD:
ESTRT:
CNT:
RSVD
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
P3 --> D3
P[2:0] --> D[2:0]
SPCLK --> E
Smart Panel R/W and RS signals must be implemented
via GPIOs and controlled via software.
Reserved - Unknown during read
Enable Start - Read/Write
The Enable Signal Start Value for the parallel interface
down counter should be written to this field. When the
parallel interface counter counts down to this value during
a write cycle (see RD bit in the
cycle), the E enable signal on the E pin goes active.
The E enable signal becomes inactive just before the
counter counts down to 0x0, although data remains driven
on the D[7:0] pins throughout the 0x0 count. This allows
data to be driven for one additional clock cycle, providing
data hold time to the Smart Panel.
Count - Read/Write
The counter preload value that is written to this field gets
loaded into the parallel interface down counter. When a
write or read cycle is initiated by writing to the RD bit in the
ParllIfOut
this value.
Raster Engine With Analog/LCD Integrated Timing and Interface
24
8
register, the counter begins to count down from
23
7
VideoAttribs
22
6
ESTRT
21
5
register, is used to access a
20
4
ParllIfOut
DAT
19
3
EP93xx User’s Guide
register for write
18
2
CNT
17
1
16
7-61
0
7
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