EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 340
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (13Mb)
9
9-38
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
9.2.5.1 Interrupt Processing
9.2.5.2 Receive Queue Processing
9.2.5.3 Transmit Queue Processing
9.2.5.4 Other Processing
This is the suggested method for processing an interrupt:
The upper three bytes of the Interrupt Status register provide the specific information related
to the “Other” bit in the LSB. There are a number of bits that relate to the descriptor queues.
14.Wait for RxAct (BMSts) to be set, and then enqueue the receive descriptors and status.
15.Set the required values for Individual Address and Hash Table.
16.Set the required options in RXCtl and TXCtl, enabling SRxON, and STxON.
17.Set any required options in the PHY, and activate.
18.Enqueue transmit descriptors as required.
1. Interrupt received from the LAN Controller. This may be determined directly by vectoring
2. Read the Interrupt Status Clear register. Based on the result of the low byte, one or more
1. Read the RXStsQCurAdd. This is the point to which the Host needs to process the
2. Read status entries up to the value of RXStsQCurAdd.
3. For each status entry, process the receive data. Set the respective status entry to 0 after
4. Write the number of statuses processed to the RXStsEnq.
5. Write the number of descriptors returned to the RXDEnq. Writing once to each enqueue
1. Read TXStsQCurAdd. This is the point to which the Host needs to process the status
2. Read status entries up to the value of the TXStsQCurAdd.
3. For each status entry, free the data buffer.
to the interrupt service routine, or in a shared environment by polling the interrupt status
register.
status queue.
queue.
This will trigger bus master activity for the descriptor reads.
of three processes need to run - receive queue processing, transmit queue processing,
or other processing.
the data has been processed
register is more economical on bus cycles than writing once for every descriptor or
status entry. Writing once also avoids any possible delays that may otherwise occur
when the controller has to process multiple accesses to the same descriptor.
Copyright 2007 Cirrus Logic
DS785UM1
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