EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 588
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
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Part Number
Manufacturer
Quantity
Price
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16
UART3ModemCtrl
16-12
UART3 With HDLC Encoder
EP93xx User’s Guide
31
15
Default:
Definition:
Bit Descriptions:
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x0000_0000
UART3 DMA Control Register
RSVD:
DMAERR:
TXDMAE:
RXDMAE:
0x808E_0100 - Read/Write
0x0000_0000
Modem Control Register. Only the OUT1 and OUT2 bits have functionality in
UART3. The RTS and DTR bits exist but have no function.
RSVD:
OUT2:
OUT1:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
RX DMA error handing enable. If 0, the RX DMA interface
ignores error conditions in the UART receive section. If 1,
the DMA interface stops and notifies the DMA block when
an error occurs. Errors include break errors, parity errors,
and framing errors.
TX DMA interface enable. Setting to 1 enables the private
DMA interface to the transmit FIFO.
RX DMA interface enable. Setting to 1 enables the private
DMA interface to the receive FIFO.
Reserved. Unknown During Read.
OUT2 function. Controls the TENn output behavior:
1 = TENn is driven by the UART3Flag.BUSY status bit;
that is, TENn is low whenever the UART has transmit data
to send.
0 = TENn is controlled by the OUT1 bit.
OUT1 function. When OUT2 = “0”, then TENn = OUT1.
Otherwise OUT1 is ignored.
24
8
RSVD
23
7
22
6
0
21
5
RSVD
20
4
OUT2
19
3
OUT1
18
2
17
1
DS785UM1
RSVD
16
0
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