EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 139
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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DS785UM1
5.2 Registers
0x8093_000C
0x8093_001C
0x8093_008C
0x8093_009C
0x8093_00A0
0x8093_00C0
0x8093_0000
0x8093_0004
0x8093_0008
0x8093_0018
0x8093_0020
0x8093_0024
0x8093_0040
0x8093_0044
0x8093_0050
0x8093_0054
0x8093_0058
0x8093_0080
0x8093_0084
0x8093_0088
0x8093_0090
0x8093_0094
Address
This section contains the detailed register descriptions for registers in the Syscon block.
Table 5-5
for each register.
shows the address map for the registers in this block, followed by a detailed listing
KeyTchClkDiv
BootModeClr
ScratchReg0
ScratchReg1
SysSWLock
BusMstrArb
DeviceCfg
MIRClkDiv
VidClkDiv
I2SClkDiv
APBWait
Standby
ClkSet1
ClkSet2
PwrCnt
SysCfg
Name
PwrSts
STFClr
ChipID
TEOI
Halt
-
SW Locked
Yes
Yes
Yes
Yes
Yes
Yes
Yes
No
No
No
No
No
No
No
No
No
No
No
No
No
No
-
Table 5-5. Syscon Register List
Copyright 2007 Cirrus Logic
Type
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
W
W
W
R
R
R
-
Size
1 bit
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
32
-
Reading this location enters Standby mode.
MIR Clock Divider, divides MIR clock for
Reading this location enters Halt mode.
Write to clear CLDFLG, RSTFLG and
Keyscan/Touch Clock Divider
Clock/Debug control status
Write to clear Tick interrupt
Boot Mode Clear register
Power/state control state
I
Software Lock Register
Bus Master Arbitration
2
Clock speed control 1
Clock speed control 2
System Configuration
Device configuration
S Audio Clock Divider
Video Clock Divider
Scratch register 0
Scratch register 1
Chip ID Register
Description
WDTFLG.
Reserved
MIR IrDA
APB wait
EP93xx User’s Guide
System Controller
5-13
5
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