EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 585
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 585 of 824
- Download datasheet (13Mb)
UART3Flag
DS785UM1
31
15
Address:
Default:
Definition:
Bit Descriptions:
30
14
29
13
28
12
0x808E_0018 - Read/Write
0x0000_0000
UART3 Flag Register
RSVD:
TXFE:
RXFF:
TXFF:
RXFE:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Transmit FIFO Empty. The meaning of this bit depends on
the state of the FEN bit in the UART3LinCtrlHigh register.
If the FIFO is disabled, this bit is set when the transmit
holding register is empty. If the FIFO is enabled, the TXFE
bit is set when the transmit FIFO is empty.
Receive FIFO Full. The meaning of this bit depends on the
state of the FEN bit in the UART3LinCtrlHigh register. If
the FIFO is disabled, this bit is set when the receive
holding register is full. If the FIFO is enabled, the RXFF bit
is set when the receive FIFO is full.
Transmit FIFO Full. The meaning of this bit depends on
the state of the FEN bit in the UART3LinCtrlHigh register.
If the FIFO is disabled, this bit is set when the transmit
holding register is full. If the FIFO is enabled, the TXFF bit
is set when the transmit FIFO is full.
Receive FIFO Empty. The meaning of this bit depends on
the state of the FEN bit in the UART3LinCtrlHigh register.
If the FIFO is disabled, this bit is set when the receive
holding register is empty. If the FIFO is enabled, the RXFE
bit is set when the receive FIFO is empty.
24
8
RSVD
TXFE
23
7
RXFF
22
6
TXFF
21
5
RXFE
20
4
UART3 With HDLC Encoder
BUSY
19
3
EP93xx User’s Guide
DCD
18
2
DSR
17
1
CTS
16
16-9
0
16
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