EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 784
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
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Part Number
Manufacturer
Quantity
Price
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27
IDEDataIn
IDEMDMADataOut
27-14
IDE Interface
EP93xx User’s Guide
31
15
31
15
Address:
Default:
Definition:
Bit Descriptions:
Address:
Default:
Definition:
30
14
30
14
29
13
29
13
28
12
28
12
0x800A_0014 - Read Only
0x0000_0000
In PIO mode read operation, this register is the Input Data Registers,
containing the register contents or the data read from the device. The register
is loaded from the DD pins at the positive edge of the DIORn signal. The
register is read only in this operation. In MDMA and UDMA data-in operations,
this register is an exact copy of the data in the input buffer to be transferred
through DMA. The register is read only in these operations. Any write to this
register is ignored.
IDEDD:
0x800A_0018 - Write Only (should be written by the DMA controller only)
0x0000_0000
In MDMA data-out operations, this register contains the data in the output
buffer to be transferred to the device. The data is written into this register by
the DMA controller. This register should only be addressed and written by the
27
27
11
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
IDE input data in PIO read, data in input buffer in MDMA
and data at the head of input buffer in UDMA mode.
24
24
8
8
IDEDD
IDEDD
IDEDD
IDEDD
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
19
19
3
3
18
18
2
2
17
17
1
1
DS785UM1
16
16
0
0
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