EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 397
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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DS785UM1
10.1.3 DMA Operations
10.1.3.1 Memory-to-Memory Channels
The DMA controller memory-to-memory channels can also be used in “Memory to External
Peripheral” mode with handshaking protocol. A set of external handshake signals DREQ,
DACK and TC/DEOT are provided for each of 2 M2M channels.
Transfer is completed either on DEOT being asserted by the external peripheral or the byte
count expiring. Status bits will indicate if the actual byte count is equal to the programmed
limit, and also if the count was terminated by peripheral asserting DEOT. Completion of
transfer will cause a DMA interrupt on that channel and rollover to the “other” buffer
descriptor if configured.
For byte or word wide peripherals, the DMA will be programmed to request byte or word wide
AHB transfers respectively. The DMA will not issue an AHB HREQ for a transfer until it has
sampled DREQ asserted after DACK of the previous transfer has been asserted for the
duration of the programmed wait states in the SMC (and possibly DREQ is sampled in the
cycle DACK is deasserted).
The operation of the DMA controller can be defined in terms of channel functionality. Two
types of channels exist:
The two M2M channels support data transfers between:
• DREQ (input) can be programmed edge or level active, and active high or low. The
• DACK (output) can be programmed active high or low. DACK will cycle with each read
• TC/DEOT is a bidirectional signal, the direction and the active sense is programmable.
• Memory-to-Memory (M2M) channel
• Memory-to/from-Internal-Peripheral (M2P/P2M) channel.
• Memory locations which may be located in any accessible system memory banks.
• Memory locations related to IDE or SSP.
peripheral may hold DREQ active for the duration of the block transfers or may
assert/deassert on each transfer.
or write, the timing is to coincide with the nOE or nWE of the EBI.
When configured as an output, the DMA will assert TC (Terminal Count) on the final
transfer to coincide with the DACK, typically when the byte count has expired. When
configured as an input, the peripheral must assert DEOT concurrent with DREQ for the
final transfer in the block.
transfer will begin as soon as the channel is configured and enabled for memory to
memory move. For this transfer type, the DMA first fills the internal 16-byte data bay by
initiating read accesses on the source bus. It then empties the data from the data bay to
the destination bus by initiating write accesses.
These memory to memory moves can be initiated by software, in which case the
Copyright 2007 Cirrus Logic
EP93xx User’s Guide
DMA Controller
10-3
10
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