EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 360
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
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9
9-58
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
0x8001_0024 - Read/Write
0x0000_0000
0x0000_0000
Interrupt Enable Register
RSVD:
RWIE:
RxMIE:
RxBIE:
RxSQIE:
TxLEIE:
ECIE:
TxUHIE:
Copyright 2007 Cirrus Logic
Reserved. Unknown During Read.
Remote Wake-up Interrupt Enable. Setting this bit causes
an interrupt to be generated when a remote wake-up
frame is detected and the MAC is in the Remote Wake-up
mode (RXCtl).
Receiver Miss Interrupt Enable. When set, this bit will
cause an interrupt whenever a complete receive frame is
discarded due to lack of storage. This may be as a result
of long bus latency or insufficient receive descriptors. The
total number of missed frames is also counted in the
RxMiss Counter.
Receive Buffer Interrupt Enable. When set, this bit will
cause an interrupt to be generated when the last available
receive descriptor has been read into the MAC.
Receive Status Queue Interrupt Enable. When this bit is
set, an interrupt will be generated when the last available
status queue entry has been written (RXStsEnq = 0).
Transmit Length Error Interrupt Enable. Setting this bit
causes an interrupt to be generated when a transmit frame
equals or exceeds the length specified in the Max Frame
Length register.
End of Chain Interrupt Enable. The end of chain interrupt
is generated when the last transmit descriptor has been
loaded into the MAC. There may still be transmit
descriptors and or transmit data remaining in the MAC at
this time.
Transmit Underrun Halt Interrupt Enable. If there is a
transmission, and the MAC runs out of data before the full
transmitted length, then there is a transmit underrun. If the
MAC is programmed to halt in this condition (Bus Master
Control), setting TxUnderrunHaltiE will cause an interrupt
to be generated.
DS785UM1
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