EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 231
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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LineCarry
EOLOffset
DS785UM1
31
15
31
15
Address: 0x8003_003C
Default: 0x0000_0000
Definition: Horizontal Line Carry Value register
Bit Descriptions:
Address: 0x8003_0230
Default: 0x0000_0000
Definition: End-of-line Offset Register.
Bit Descriptions:
30
14
30
14
RSVD
29
13
29
13
28
12
28
12
RSVD:
LCARY:
RSVD:
OFFSET:
27
11
27
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
Reserved - Unknown during read
Line Carry - Read/Write
When the Horizontal down counter counts down to the
written LCARY value, a carry is sent to increment the
Vertical counter. This provides for timing skew between
the vertical and horizontal video signals. Please refer to
the video signalling timing diagrams in
Figure
Reserved - Unknown during read
Offset - Read/Write
The Offset value written to this field is added to the
address at the end of every other video line if the Offset
value is not 0x0. This allows splitting the left and right
halves of the display.
Raster Engine With Analog/LCD Integrated Timing and Interface
24
24
8
8
OFFSET
RSVD
RSVD
7-10.
23
23
7
7
22
22
6
6
LCARY
21
21
5
5
20
20
4
4
19
19
3
3
Figure 7-9
EP93xx User’s Guide
18
18
2
2
17
17
1
1
and
16
16
7-49
0
0
7
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