EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 241
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (13Mb)
DS785UM1
S:
P:
M3
S2
P2
0
0
0
0
1
1
1
1
0
0
0
1
1
1
1
0
0
0
0
Table 7-14. Blink Mode Definition Table (Continued)
M2
S1
1
1
1
1
1
1
1
P1
0
0
1
1
0
0
1
1
0
0
1
1
Table 7-16. Bits per Pixel Scanned Out
Table 7-15. Output Shift Mode Table
M1
0
1
1
0
0
1
1
Copyright 2007 Cirrus Logic
S0
P0
0
1
0
1
0
1
0
1
0
1
0
1
Shift - Read/Write
The Shift Mode is specified by selecting a value from
Table 7-15
Pixel - Read/Write
The number of bits per pixel that are output on the P[x]
pins is specified by selecting a value from
writing it to this field.
The Graphics Engine has a separate setting for this value,
which may or may not be the same.
M0
Raster Engine With Analog/LCD Integrated Timing and Interface
1
0
1
0
1
0
1
Dual Scan 2 2/3 3-bit pixels per clock over 8-bit bus
2 - pixels per shift clock (up to 9 bits wide each)
4 - pixels per shift clock (up to 4 bits wide each)
8 - pixels per shift clock (up to 2 bits wide each)
Undefined - Defaults to 1 - pixel per pixel clock
1 - pixel mapped to 18 bits each pixel clock
1 - pixel per pixel clock (up to 24 bits wide)
2 2/3 3-bit pixels per clock over 8 bit bus
Blink to offset color 888 mode (555,565)
Blink to offset color single value mode
and writing it to this field.
pixel multiplexer disabled
Blink brighter 888 mode (555,565)
Blink dimmer 888 mode (555,565)
Blink dimmer single value mode
Blink brighter single value mode
4 bits per pixel
8 bits per pixel
Pixel Mode
Shift Mode
do not use
Blink Mode
Undefined
EP93xx User’s Guide
Table 7-16
and
7-59
7
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