EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 453
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
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Part Number
Manufacturer
Quantity
Price
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- Download datasheet (13Mb)
DS785UM1
Definition:
Bit Descriptions:
Controls the host controller’s operating modes.
RSVD:
CBSR:
PLE:
IE:
CLE:
Copyright 2007 Cirrus Logic
Reserved. Unknown During Read.
ControlBulkServiceRatio:
This specifies the service ratio between Control and Bulk
EDs. Before processing any of the nonperiodic lists, HC
must compare the ratio specified with its internal count on
how many nonempty Control EDs have been processed,
in determining whether to continue serving another Control
ED or switching to Bulk EDs. The internal count will be
retained when crossing the frame boundary. In case of
reset, HCD is responsible for restoring this value.
0 0 = 1:1
0 1 = 2:1
1 0 = 3:1
1 1 = 4:1
PeriodicListEnable:
This bit is set to enable the processing of the periodic list
in the next Frame. If cleared by HCD, processing of the
periodic list does not occur after the next SOF. HC must
check this bit before it starts processing the list.
IsochronousEnable:
This bit is used by HCD to enable/disable processing of
isochronous EDs. While processing the periodic list in a
Frame, HC checks the status of this bit when it finds an
Isochronous ED (F=1). If set (enabled), HC continues
processing the EDs. If cleared (disabled), HC halts
processing of the periodic list (which now contains only
isochronous EDs) and begins processing the Bulk/Control
lists. Setting this bit is guaranteed to take effect in the next
Frame (not the current Frame).
ControlListEnable:
This bit is set to enable the processing of the Control list in
the next Frame. If cleared by HCD, processing of the
Control list does not occur after the next SOF. HC must
check this bit whenever it determines to process the list.
When disabled, HCD may modify the list. If
HcControlCurrentED is pointing to an ED to be removed,
HCD must advance the pointer by updating
HcControlCurrentED before re-enabling processing of the
list.
Universal Serial Bus Host Controller
EP93xx User’s Guide
11-13
11
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