EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 48
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (13Mb)
2
2-10
ARM920T Core and Advanced High-Speed Bus (AHB)
EP93xx User’s Guide
2.2.8.1 Main AHB Bus Arbiter
This Main AHB Bus Arbiter controls bus master arbitration for the AHB bus. The AHB bus has
eight master interfaces:
These interfaces have an order of priority that is linked closely with the power saving modes
Halt and Standby. These power saving modes force the Arbiter to grant the default bus
master, in this case, the ARM920T.
The order of priority of the bus masters, from highest to lowest, is shown in
The priority of the arbiter may be programmed via the BusMstrArb register in the Clock and
State Controller. The arbiter can also be programmed to degrant one of these masters: DMA,
USB Host or Ethernet MAC if an interrupt (IRQ or FIQ) is pending or being serviced. This
prevents one of these masters from blocking important interrupt service routines. These
masters are thereby prevented from accessing the bus, that is, their bus requests are
masked until the IRQ/FIQ is removed (by the Interrupt Service Routine). After the IRQ/FIQ is
removed, their bus requests will again be recognized. The default is to program the arbiter so
that it does not degrant any of these masters.
In normal operation, when the ARM920T is granted the bus and a request to enter Halt mode
is received, the ARM920T is de-granted from the AHB bus. Any other master requesting the
bus during Halt mode (according to it’s priority) will be granted the bus. In the case of entry
into Standby mode, the dummy master will be granted the bus, which simply performs IDLE
transfers. In this way, all the masters except the ARM920T can be used during Halt mode, but
are shutdown upon entry into Standby mode.
• ARM920T
• DMA controller
• USB hosts (USB1, 2, 3)
• Ethernet MAC
• LCD/Raster
• Raster Hardware Cursor.
Number
Priority
1
2
3
4
5
6
(Reset value)
PRIORITY 00
Raster Cursor
ARM920T
Raster
MAC
DMA
USB
Copyright 2007 Cirrus Logic
Table 2-1. AHB Arbiter Priority Scheme
PRIORITY 01
Raster Cursor
ARM920T
Raster
MAC
DMA
USB
PRIORITY 10
Raster Cursor
ARM920T
Raster
DMA
MAC
USB
PRIORITY 11
Raster Cursor
ARM920T
Table
Raster
DMA
MAC
USB
2-1.
DS785UM1
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