EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 383

• Manufacturer Part Number: EP9301-IQZ
• Description: 32-Bit Microcontroller IC
• Manufacturer: Cirrus Logic Inc
• Series: EP9r

Specifications of EP9301-IQZ

• Controller Family/series: (ARM9)
• Core Size: 32 Bit
• A/d Converter: 12 Bits
• Supply Voltage: 3.3V
• No. Of I/o Pins: 24
• Mounting Type: Surface Mount
• Operating Temperature Min: -40°C
• Package / Case: 208-LQFP
• Core Processor: ARM9
• Speed: 166MHz
• Connectivity: EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
• Peripherals: AC'97, DMA, I&sup2:S, LED, MaverickKey, POR, PWM, WDT
• Number Of I /o: 19
• Program Memory Type: ROMless
• Ram Size: 32K x 8
• Voltage - Supply (vcc/vdd): 1.65 V ~ 3.6 V
• Data Converters: A/D 5x12b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: EP93xx
• Core: ARM920T
• Data Bus Width: 32 bit
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: MDK-ARM, RL-ARM, ULINK2
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Lead Free Status / Rohs Status: Details
• Other names: 598-1250

TXDQCurAdd
DS785UM1
31
15
Soft Reset:
Definition:
Bit Descriptions:
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
30
14
29
13
28
12
Unchanged
Transmit Descriptor Queue Current Length register. The Transmit Descriptor
Queue Current Length defines the number of bytes between the Transmit
Descriptor Current Address and the end of the transmit descriptor queue. This
value is used internally to wrap the pointer back to the start of the queue. The
register should not normally be written.
RSVD:
TDCL:
0x8001_00B8 - Read/Write
0x0000_0000
Unchanged
Transmit Descriptor Queue Current Address register. The Transmit Descriptor
Queue Current Address contains the pointer to the next memory location to be
read from the transmit descriptor queue. This should be set at initialization
time to the required starting point in the descriptor queue. During operation,
the MAC will update this address following successful descriptor reads.
Intermediate values in this register will not necessarily align to descriptor
boundaries, nor directly effect the current descriptor in use because several
descriptors may be buffered inside the MAC.
TDCA:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Transmit Descriptor Current Length.
Transmit Descriptor Current Address.
24
8
TDCA
TDCA
23
7
22
6
21
1/10/100 Mbps Ethernet LAN Controller
5
20
4
19
3
EP93xx User’s Guide
18
2
17
1
16
9-81
0
9