EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 422
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- Current page: 422 of 824
- Download datasheet (13Mb)
10
REMAIN
10-28
DMA Controller
EP93xx User’s Guide
31
15
Address:
Definition:
Bit Descriptions:
30
14
29
13
28
12
Channel Base Address + 0x0014 - Read Only
The Channel Bytes Remaining Register contains the number of bytes
remaining in the current DMA transfer. Only the lower 16 bits are valid
RSVD:
REMAIN:
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Reserved. Unknown During Read.
Loaded from the Channel MAXCNT register when the
DMA Channel State Machine enters the ON State.
Although there are 2 Data transfer states, ON and NEXT,
this register need only be assigned in the ON state,
because in this state the next buffer to be used is
determined (there is only one) and this MAXCNT value is
assigned to REMAIN. The DMA State Machine counts
down by one byte every time a byte is transferred between
the DMA Controller and the Peripheral. When this register
reaches zero, the current buffer transfer is complete and
the TxTC/RxTC are generated and used to indicate this to
the peripheral. DMA transfers may also be stopped with
the TxEnd/RxEnd signals from the peripheral, where the
REMAIN register is non-zero at the end of transfer,
allowing software to determine the last valid data in a
buffer.
24
8
REMAIN
RSVD
23
7
22
6
21
5
20
4
19
3
18
2
17
1
DS785UM1
16
0
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