EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 384
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
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Part Number
Manufacturer
Quantity
Price
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9
TXDEnq
TXStsQBAdd
9-82
1/10/100 Mbps Ethernet LAN Controller
EP93xx User’s Guide
31
15
31
15
Address:
Chip Reset:
Soft Reset:
Definition:
Bit Descriptions:
Address:
Chip Reset:
30
14
30
14
29
13
29
13
28
12
28
12
0x8001_00BC - Read/Write
0x0000_0000
Unchanged
Transmit Descriptor Enqueue register. The Transmit Descriptor Enqueue
register is used to define the number of valid descriptors available in the
transmit descriptor queue. Only the Transmit descriptor Increment field is
writable and any value written to this field will be added to the existing
Transmit Descriptor Value. When complete descriptors are read by the MAC,
the Transmit Descriptor Value is decremented by the number read. For
example if the Transmit Descriptor Value is 0x07, and the Host writes 0x03 to
the Transmit Descriptor Increment, the new Value will be 0x0A. If the controller
then reads two descriptors, the Value will be 0x08.
RSVD:
TDV:
TDI:
0x8001_00C0 - Read/Write
RSVD
27
27
11
11
26
10
26
10
Copyright 2007 Cirrus Logic
25
25
9
9
Reserved. Unknown During Read.
Transmit Descriptor Value.
Transmit Descriptor Increment.
24
24
8
8
TSQBA
TSQBA
TDV
23
23
7
7
22
22
6
6
21
21
5
5
20
20
4
4
TDI
19
19
3
3
18
18
2
2
17
17
1
1
DS785UM1
16
16
0
0
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