EP9301-IQZ Cirrus Logic Inc, EP9301-IQZ Datasheet - Page 155
![32-Bit Microcontroller IC](/photos/12/23/122383/mfg_ep9301_parts_sml.jpg)
EP9301-IQZ
Manufacturer Part Number
EP9301-IQZ
Description
32-Bit Microcontroller IC
Manufacturer
Cirrus Logic Inc
Series
EP9r
Specifications of EP9301-IQZ
Controller Family/series
(ARM9)
Core Size
32 Bit
A/d Converter
12 Bits
Supply Voltage
3.3V
No. Of I/o Pins
24
Mounting Type
Surface Mount
Operating Temperature Min
-40°C
Package / Case
208-LQFP
Core Processor
ARM9
Speed
166MHz
Connectivity
EBI/EMI, Ethernet, I²C, IrDA, SPI, UART/USART, USB
Peripherals
AC'97, DMA, I²:S, LED, MaverickKey, POR, PWM, WDT
Number Of I /o
19
Program Memory Type
ROMless
Ram Size
32K x 8
Voltage - Supply (vcc/vdd)
1.65 V ~ 3.6 V
Data Converters
A/D 5x12b
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Processor Series
EP93xx
Core
ARM920T
Data Bus Width
32 bit
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Details
Other names
598-1250
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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- Download datasheet (13Mb)
VidClkDiv
DS785UM1
VENA
31
15
Address:
Default:
Definition:
Bit Descriptions:
ESEL
30
14
PSEL
29
13
28
12
SWRST:
0x8093_0084 - Read/Write, Software locked
0x0000_0000
Configures video clock for the raster engine. Selects input to VCLK dividers
from either PLL1 or PLL2, and defines a programmable divide value.
RSVD:
VENA:
ESEL:
PSEL:
PDIV:
VDIV:
RSVD
27
11
26
10
Copyright 2007 Cirrus Logic
25
9
Software reset. A one to zero transition of this bit initiates
a software reset.
Reserved. Unknown During Read.
Enable VCLK divider.
External clock source select.
0 - use the external XTALI clock input as the clock source.
1 - use one of the internal PLLs selected by PSEL as the
clock source.
PLL source select.
1 - select PLL2 as the clock source.
0 - select PLL1 as the clock source.
Pre-divider value. Generates divide by 2, 2.5, or 3 from the
clock source.
00 - Disable clock
01 - Divide-by-2
10 - Divide-by-2.5
11 - Divide-by-3
VCLK divider value. Forms a divide-by-N of the pre-divide
clock output. VCLK is the source clock divided by PDIV
divided by N. Must be at least two.
PDIV
24
8
RSVD
RSVD
23
7
22
6
21
5
20
4
VDIV
19
3
EP93xx User’s Guide
System Controller
18
2
17
1
16
5-29
0
5
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