ATMEGA128RZBV-8AU Atmel, ATMEGA128RZBV-8AU Datasheet - Page 85

• Manufacturer Part Number: ATMEGA128RZBV-8AU
• Description: MCU ATMEGA1280/AT86RF230 100TQFP
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RZBV-8AU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 8kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 100-TQFP
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega128

2549M–AVR–09/10
Table 12-13. Overriding Signals for Alternate Functions PD7:PD4
Table 12-14. Overriding Signals for Alternate Functions in PD3:PD0
Note:
Signal Name
Signal Name
DIEOE
DIEOV
DDOE
PUOE
PUOV
DDOV
PVOE
PVOV
DIEOE
DIEOV
DDOE
PUOE
PUOV
DDOV
PVOE
PVOV
AIO
AIO
DI
DI
1. When enabled, the 2-wire Serial Interface enables Slew-Rate controls on the output pins PD0
and PD1. This is not shown in this table. In addition, spike filters are connected between the
AIO outputs shown in the port figure and the digital logic of the TWI module.
PD3/INT3/TXD1
INT3 ENABLE
INT3 INPUT
T0 INPUT
PD7/T0
TXEN1
TXEN1
TXEN1
TXD1
0
0
0
0
0
0
0
0
–
0
1
1
–
ATmega640/1280/1281/2560/2561
T1 INPUT
PD6/T1
INT2 INPUT/RXD1
PD2/INT2/RXD1
PORTD2 • PUD
INT2 ENABLE
0
0
0
0
0
0
0
0
–
RXEN1
RXEN1
0
0
0
1
–
XCK1 OUTPUT ENABLE
XCK1 OUTPUT ENABLE
XCK1 OUTPUT
XCK1 INPUT
PD5/XCK1
PORTD1 • PUD
PD1/INT1/SDA
INT1 ENABLE
INT1 INPUT
SDA INPUT
SDA_OUT
0
0
1
0
0
–
TWEN
TWEN
TWEN
0
1
(1)
PORTD0 • PUD
PD0/INT0/SCL
INT0 ENABLE
INT0 INPUT
SCL INPUT
SCL_OUT
ICP1 INPUT
TWEN
TWEN
TWEN
PD4/ICP1
0
1
0
0
0
0
0
0
0
0
–
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