ATMEGA128RZBV-8AU Atmel, ATMEGA128RZBV-8AU Datasheet - Page 265

• Manufacturer Part Number: ATMEGA128RZBV-8AU
• Description: MCU ATMEGA1280/AT86RF230 100TQFP
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RZBV-8AU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 8kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 100-TQFP
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega128

23.8
2549M–AVR–09/10
Multi-master Systems and Arbitration
Note that data is transmitted both from Master to Slave and vice versa. The Master must instruct
the Slave what location it wants to read, requiring the use of the MT mode. Subsequently, data
must be read from the Slave, implying the use of the MR mode. Thus, the transfer direction must
be changed. The Master must keep control of the bus during all these steps, and the steps
should be carried out as an atomical operation. If this principle is violated in a multimaster sys-
tem, another Master can alter the data pointer in the EEPROM between steps 2 and 3, and the
Master will read the wrong data location. Such a change in transfer direction is accomplished by
transmitting a REPEATED START between the transmission of the address byte and reception
of the data. After a REPEATED START, the Master keeps ownership of the bus. The following
figure shows the flow in this transfer.
Figure 23-19. Combining Several TWI Modes to Access a Serial EEPROM
If multiple masters are connected to the same bus, transmissions may be initiated simultane-
ously by one or more of them. The TWI standard ensures that such situations are handled in
such a way that one of the masters will be allowed to proceed with the transfer, and that no data
will be lost in the process. An example of an arbitration situation is depicted below, where two
masters are trying to transmit data to a Slave Receiver.
Figure 23-20. An Arbitration Example
Several different scenarios may arise during arbitration, as described below:
•
•
Two or more masters are performing identical communication with the same Slave. In this
case, neither the Slave nor any of the masters will know about the bus contention.
Two or more masters are accessing the same Slave with different data or direction bit. In this
case, arbitration will occur, either in the READ/WRITE bit or in the data bits. The masters
trying to output a one on SDA while another Master outputs a zero will lose the arbitration.
Losing masters will switch to not addressed Slave mode or wait until the bus is free and
transmit a new START condition, depending on application software action.
S
S = START
SDA
SCL
Transmitted from master to slave
SLA+W
TRANSMITTER
Device 1
MASTER
A
Master Transmitter
ADDRESS
TRANSMITTER
ATmega640/1280/1281/2560/2561
Device 2
MASTER
Device 3
RECEIVER
A
SLAVE
Rs = REPEATED START
Rs
Transmitted from slave to master
........
SLA+R
Device n
V
CC
A
Master Receiver
R1
DATA
R2
P = STOP
A
P
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