ATMEGA128RZBV-8AU Atmel, ATMEGA128RZBV-8AU Datasheet - Page 167

• Manufacturer Part Number: ATMEGA128RZBV-8AU
• Description: MCU ATMEGA1280/AT86RF230 100TQFP
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RZBV-8AU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 8kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 100-TQFP
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega128

16.11.37 TIFR1 – Timer/Counter1 Interrupt Flag Register
16.11.38 TIFR3 – Timer/Counter3 Interrupt Flag Register
16.11.39 TIFR4 – Timer/Counter4 Interrupt Flag Register
16.11.40 TIFR5 – Timer/Counter5 Interrupt Flag Register
2549M–AVR–09/10
• Bit 1 – OCIEnA: Timer/Countern, Output Compare A Match Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Output Compare A Match interrupt is enabled. The corresponding
Interrupt Vector (see
TIFRn, is set.
• Bit 0 – TOIEn: Timer/Countern, Overflow Interrupt Enable
When this bit is written to one, and the I-flag in the Status Register is set (interrupts globally
enabled), the Timer/Countern Overflow interrupt is enabled. The corresponding Interrupt Vector
(see
• Bit 5 – ICFn: Timer/Countern, Input Capture Flag
This flag is set when a capture event occurs on the ICPn pin. When the Input Capture Register
(ICRn) is set by the WGMn3:0 to be used as the TOP value, the ICFn Flag is set when the coun-
ter reaches the TOP value.
ICFn is automatically cleared when the Input Capture Interrupt Vector is executed. Alternatively,
ICFn can be cleared by writing a logic one to its bit location.
• Bit 3– OCFnC: Timer/Countern, Output Compare C Match Flag
This flag is set in the timer clock cycle after the counter (TCNTn) value matches the Output
Compare Register C (OCRnC).
Note that a Forced Output Compare (FOCnC) strobe will not set the OCFnC Flag.
OCFnC is automatically cleared when the Output Compare Match C Interrupt Vector is exe-
cuted. Alternatively, OCFnC can be cleared by writing a logic one to its bit location.
Bit
0x16 (0x36)
Read/Write
Initial Value
Bit
0x18 (0x38)
Read/Write
Initial Value
Bit
0x19 (0x39)
Read/Write
Initial Value
Bit
0x1A (0x3A)
Read/Write
Initial Value
“Interrupts” on page
R
R
R
R
7
–
0
7
–
0
7
–
0
7
–
0
“Interrupts” on page
105) is executed when the TOVn Flag, located in TIFRn, is set.
R
R
R
R
6
–
0
6
–
0
6
–
0
6
–
0
ATmega640/1280/1281/2560/2561
ICF1
ICF3
ICF4
ICF5
R/W
R/W
R/W
R/W
5
0
5
0
5
0
5
0
105) is executed when the OCFnA Flag, located in
R
R
R
R
4
–
0
4
–
0
4
–
0
4
–
0
OCF1C
OCF3C
OCF4C
OCF5C
R/W
R/W
R/W
R/W
3
0
3
0
3
0
3
0
OCF1B
OCF3B
OCF4B
OCF5B
R/W
R/W
R/W
R/W
2
0
2
0
2
0
2
0
OCF1A
OCF3A
OCF4A
OCF5A
R/W
R/W
R/W
R/W
1
0
1
0
1
0
1
0
TOV1
TOV3
TOV4
TOV5
R/W
R/W
R/W
R/W
0
0
0
0
0
0
0
0
TIFR1
TIFR3
TIFR4
TIFR5
167