ATMEGA128RZBV-8AU Atmel, ATMEGA128RZBV-8AU Datasheet - Page 205

• Manufacturer Part Number: ATMEGA128RZBV-8AU
• Description: MCU ATMEGA1280/AT86RF230 100TQFP
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RZBV-8AU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 8kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 100-TQFP
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega128

21. USART
21.1
Overview
2549M–AVR–09/10
Features
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The Universal Synchronous and Asynchronous serial Receiver and Transmitter (USART) is a
highly flexible serial communication device.
The ATmega640/1280/2560 has four USART’s, USART0, USART1, USART2, and USART3.
The functionality for all four USART’s is described below. USART0, USART1, USART2, and
USART3 have different I/O registers as shown in
A simplified block diagram of the USART Transmitter is shown in
accessible I/O Registers and I/O pins are shown in bold.
The Power Reducion USART0 bit, PRUSART0, in
page 56
The Power Reducion USART1 bit, PRUSART1, in
page 57
The Power Reducion USART2 bit, PRUSART2, in
page 57
The Power Reducion USART3 bit, PRUSART3, in
page 57
Full Duplex Operation (Independent Serial Receive and Transmit Registers)
Asynchronous or Synchronous Operation
Master or Slave Clocked Synchronous Operation
High Resolution Baud Rate Generator
Supports Serial Frames with 5, 6, 7, 8, or 9 Data Bits and 1 or 2 Stop Bits
Odd or Even Parity Generation and Parity Check Supported by Hardware
Data OverRun Detection
Framing Error Detection
Noise Filtering Includes False Start Bit Detection and Digital Low Pass Filter
Three Separate Interrupts on TX Complete, TX Data Register Empty and RX Complete
Multi-processor Communication Mode
Double Speed Asynchronous Communication Mode
must be disabled by writing a logical zero to it.
must be disabled by writing a logical zero to it.
must be disabled by writing a logical zero to it.
must be disabled by writing a logical zero to it.
ATmega640/1280/1281/2560/2561
“Register Summary” on page
“PRR0 – Power Reduction Register 0” on
“PRR1 – Power Reduction Register 1” on
“PRR1 – Power Reduction Register 1” on
“PRR1 – Power Reduction Register 1” on
Figure 21-1 on page
410.
206. CPU
205