ATMEGA128RZBV-8AU Atmel, ATMEGA128RZBV-8AU Datasheet - Page 207

• Manufacturer Part Number: ATMEGA128RZBV-8AU
• Description: MCU ATMEGA1280/AT86RF230 100TQFP
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RZBV-8AU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 8kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 100-TQFP
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega128

21.2.1
2549M–AVR–09/10
Internal Clock Generation – The Baud Rate Generator
UCSRnA Register. When using synchronous mode (UMSELn = 1), the Data Direction Register
for the XCKn pin (DDR_XCKn) controls whether the clock source is internal (Master mode) or
external (Slave mode). The XCKn pin is only active when using synchronous mode.
Figure 21-2
Figure 21-2. Clock Generation Logic, Block Diagram
Signal description:
Internal clock generation is used for the asynchronous and the synchronous master modes of
operation. The description in this section refers to
The USART Baud Rate Register (UBRRn) and the down-counter connected to it function as a
programmable prescaler or baud rate generator. The down-counter, running at system clock
(f
the UBRRLn Register is written. A clock is generated each time the counter reaches zero. This
clock is the baud rate generator clock output (= f
baud rate generator clock output by 2, 8 or 16 depending on mode. The baud rate generator out-
put is used directly by the Receiver’s clock and data recovery units. However, the recovery units
use a state machine that uses 2, 8 or 16 states depending on mode set by the state of the
UMSELn, U2Xn and DDR_XCKn bits.
Table 21-1 on page 208
for calculating the UBRRn value for each mode of operation using an internally generated clock
source.
osc
), is loaded with the UBRRn value each time the counter has counted down to zero or when
txclk
rxclk
xcki
xcko
f
OSC
DDR_XCK
XCK
Pin
shows a block diagram of the clock generation logic.
xcko
xcki
OSC
operation.
operation.
Transmitter clock (Internal Signal).
Receiver base clock (Internal Signal).
Input from XCK pin (internal Signal). Used for synchronous slave
Clock output to XCK pin (Internal Signal). Used for synchronous master
XTAL pin frequency (System Clock).
Down-Counter
Prescaling
contains equations for calculating the baud rate (in bits per second) and
Register
UBRR
Sync
ATmega640/1280/1281/2560/2561
UBRR+1
fosc
Detector
UCPOL
Edge
/2
Figure
osc
/(UBRRn+1)). The Transmitter divides the
/4
21-2.
/2
DDR_XCK
U2X
0
1
0
1
0
1
1
0
UMSEL
txclk
rxclk
207