ATMEGA128RZBV-8AU Atmel, ATMEGA128RZBV-8AU Datasheet - Page 29

• Manufacturer Part Number: ATMEGA128RZBV-8AU
• Description: MCU ATMEGA1280/AT86RF230 100TQFP
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RZBV-8AU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 8kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 100-TQFP
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega128

8.1.1
8.1.2
2549M–AVR–09/10
Using the External Memory Interface
Address Latch Requirements
The interface consists of:
•
•
•
•
The control bits for the External Memory Interface are located in two registers, the External
Memory Control Register A – XMCRA, and the External Memory Control Register B – XMCRB.
When the XMEM interface is enabled, the XMEM interface will override the setting in the data
direction registers that corresponds to the ports dedicated to the XMEM interface. For details
about the port override, see the alternate functions in section
interface will auto-detect whether an access is internal or external. If the access is external, the
XMEM interface will output address, data, and the control signals on the ports according to
ure 8-3 on page 31
high-to-low, there is a valid address on AD7:0. ALE is low during a data transfer. When the
XMEM interface is enabled, also an internal access will cause activity on address, data and ALE
ports, but the RD and WR strobes will not toggle during internal access. When the External
Memory Interface is disabled, the normal pin and data direction settings are used. Note that
when the XMEM interface is disabled, the address space above the internal SRAM boundary is
not mapped into the internal SRAM.
SRAM to the AVR using an octal latch (typically “74 × 573” or equivalent) which is transparent
when G is high.
Due to the high-speed operation of the XRAM interface, the address latch must be selected with
care for system frequencies above 8 MHz @ 4V and 4 MHz @ 2.7V. When operating at condi-
tions above these frequencies, the typical old style 74HC series latch becomes inadequate. The
External Memory Interface is designed in compliance to the 74AHC series latch. However, most
latches can be used as long they comply with the main timing parameters. The main parameters
for the address latch are:
•
•
•
The External Memory Interface is designed to guaranty minimum address hold time after G is
asserted low of t
9 through Tables 30-16 on pages 378 - 381. The D-to-Q propagation delay (t
into consideration when calculating the access time requirement of the external component. The
data setup time before G low (t
wiring delay (dependent on the capacitive load).
AD7:0: Multiplexed low-order address bus and data bus.
ALE: Address latch enable.
RD: Read strobe.
WR: Write strobe.
D to Q propagation delay (t
Data setup time before G low (t
Data (address) hold time after G low (
• A15:8: High-order address bus (configurable number of bits).
h
= 5 ns. Refer to t
(this figure shows the wave forms without wait-states). When ALE goes from
SU
PD
ATmega640/1280/1281/2560/2561
) must not exceed address valid to ALE low (t
).
LAXX_LD
SU
Figure 8-2 on page 30
).
/t
TH
LLAXX_ST
).
in “External Data Memory Timing” Tables 30-
illustrates how to connect an external
“I/O-Ports” on page
PD
AVLLC
) must be taken
70. The XMEM
) minus PCB
Fig-
29