ATMEGA128RZBV-8AU Atmel, ATMEGA128RZBV-8AU Datasheet - Page 307

• Manufacturer Part Number: ATMEGA128RZBV-8AU
• Description: MCU ATMEGA1280/AT86RF230 100TQFP
• Manufacturer: Atmel
• Series: ATMEGAr

Specifications of ATMEGA128RZBV-8AU

• Frequency: 2.4GHz
• Data Rate - Maximum: 2Mbps
• Modulation Or Protocol: 802.15.4 Zigbee
• Applications: General Purpose
• Power - Output: 3dBm
• Sensitivity: -101dBm
• Voltage - Supply: 1.8 V ~ 3.6 V
• Data Interface: PCB, Surface Mount
• Memory Size: 128kB Flash, 4kB EEPROM, 8kB RAM
• Antenna Connector: PCB, Surface Mount
• Package / Case: 100-TQFP
• Wireless Frequency: 2.4 GHz
• Interface Type: JTAG, SPI
• Output Power: 3 dBm
• For Use With: ATAVRISP2 - PROGRAMMER AVR IN SYSTEMATSTK501 - ADAPTER KIT FOR 64PIN AVR MCUATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Operating Temperature: -
• Current - Transmitting: -
• Current - Receiving: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• For Use With/related Products: ATmega128

27.5.2
2549M–AVR–09/10
Scanning the RESET Pin
Figure 27-4. General Port Pin Schematic Diagram
The RESET pin accepts 5V active low logic for standard reset operation, and 12V active high
logic for High Voltage Parallel programming. An observe-only cell as shown in
inserted for the 5V reset signal.
Figure 27-5. Observe-only Cell
See Boundary-scan
Description for Details!
Pxn
From System Pin
PUD:
PUExn:
OCxn:
ODxn:
IDxn:
SLEEP:
IDxn
ATmega640/1280/1281/2560/2561
PULLUP DISABLE
PULLUP ENABLE for pin Pxn
OUTPUT CONTROL for pin Pxn
OUTPUT DATA to pin Pxn
INPUT DATA from pin Pxn
SLEEP CONTROL
Previous
From
PUExn
Cell
ShiftDR
0
1
ClockDR
SLEEP
OCxn
ODxn
D
FF1
SYNCHRONIZER
WDx:
RDx:
WRx:
RRx:
RPx:
CLK
D
L
Q
Q
Q
Next
I/O
Cell
To
:
D
WRITE DDRx
READ DDRx
WRITE PORTx
READ PORTx REGISTER
READ PORTx PIN
I/O CLOCK
PINxn
Q
Q
To System Logic
RESET
RESET
Q
Q
Q
Q
PORTxn
DDxn
CLR
CLR
D
D
CLK
PUD
WDx
RDx
WRx
RPx
RRx
I/O
Figure 27-5
307
is