UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 963
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3768GF-GAT-AX
Manufacturer Part Number
UPD70F3768GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3768GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3768GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 963 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(29) UF0 FIFO clear 0 register (UF0FIC0)
Remark
UF0FIC0
Bit position
This register clears each FIFO.
This register is write-only, in 8-bit units. If this register is read, 00H is read.
FW can clear the target FIFO by writing 1 to the corresponding bit of this register. The bit to which 1 has been
written is automatically cleared to 0. Writing 0 to the bit is invalid.
The related bits are invalid if each endpoint is not supported by the setting of the UF0EnIM register (n = 1, 3, 7)
and the current setting of the interface.
7, 5
6, 4
2
1
0
n = 1, 2
m = 1 when n = 1
m = 3 when n = 2
BKI2SC
7
BKInSC
BKInCC
ITR1C
EP0WC
EP0RC
Bit name
BKI2CC
6
BKI1SC
These bits clear only the FIFO on the SIE side of the UF0BIn register (reset the counter).
Writing these bits is invalid while an IN token for Endpoint m is being processed with the
BKInNK bit set to 1.
The BKInNK bit is automatically cleared to 0 by clearing the FIFO. Make sure that the
FIFO on the CPU side is empty when these bits are used.
These bits clear only the FIFO on the CPU side of the UF0BIn register (reset the counter).
These bits clear the UF0INT1 register (reset the counter).
Writing these bits is invalid while an IN token for Endpoint 7 is being processed with the
IT1NK bit set to 1.
The IT1NK bit is automatically cleared to 0 by clearing the FIFO.
This bit clears the UF0E0W register (resets the counter).
Writing this bit is invalid while an IN token for Endpoint0 is being processed with the
EP0NKW bit set to 1.
The EP0NKW bit is automatically cleared to 0 by clearing the FIFO.
This bit clears the UF0E0R register (resets the counter).
When the EP0NKR bit is set to 1 (except when it has been set by FW), the EP0NKR bit is
automatically cleared to 0 by clearing the FIFO.
5
1: Clear
1: Clear
1: Clear
1: Clear
1: Clear
BKI1CC
4
3
0
CHAPTER 20 USB FUNCTION CONTROLLER (USBF)
ITR1C
2
Function
EP0WC
1
EP0RC
0
00200060H
Address
Page 963 of 1408
After reset
00H
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