UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 216
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UPD70F3768GF-GAT-AX
Manufacturer Part Number
UPD70F3768GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3768GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3768GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 216 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(2) TAAn control register 1 (TAAnCTL1)
The TAAnCTL1 register is an 8-bit register that controls the operation of TAAn.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
TAA0CTL1
TAA1CTL1
TAA2CTL1
TAA3CTL1
TAA4CTL1
TAA5CTL1
After reset: 00H
Cautions 1. The TAAnEST bit is valid only in the external trigger pulse output
TAAmSYE
TAA0SYE
TAA2SYE
TAA4SYE
TAA5SYE
TAAnEST
These bits can be set only for the slave timer (setting them for the master timer is
prohibited).
The relationship between the master timer and slave timer is as follows.
For the tuned-operation function, see 7.6 Timer-Tuned Operation Function.
For the simultaneous-start function, see 7.7 Simultaneous-Start Function.
0
0
1
1
0
0
0
1
7
TAAmSYM
TAA0EST TAA0EEETAA0SYM
TAA1EST TAA1EEE
TAA2EST TAA2EEETAA2SYM
TAA3EST TAA3EEE
TAA5EST TAA5EEETAA5SYM
Generates a valid signal for external trigger input.
• In one-shot pulse output mode:
• In external trigger pulse output mode:
2. Be sure to clear the sections of the TAAnCTL1 register of each
R/W
Master timer
A one-shot pulse is output with writing 1 to the TAAnEST bit as the trigger.
A PWM waveform is output with writing 1 to the TAAnEST bit as the trigger.
0
1
0
1
mode or one-shot pulse output mode. In any other mode, writing 1
to this bit is ignored.
channel, where 0 is specified, to 0.
6
0
TAA1
TAA3
TAB0
TAB1
Address:
Independent operation mode (asynchronous operation mode)
Setting prohibited
Tuned-operation function (specification of slave operation)
Simultaneous-start function (specification of slave timer)
Tuned operation mode enable control (m = 0, 2, 4, 5)
5
0
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Software trigger control (n = 0 to 3, 5)
TAA4SYM
TAA0CTL1 FFFFF631H, TAA1CTL1 FFFFF641H,
TAA2CTL1 FFFFF651H, TAA3CTL1 FFFFF661H,
TAA4CTL1 FFFFF671H, TAA5CTL1 FFFFF681H
Slave timer
4
0
0
TAA0
TAA2
TAA5
TAA4
−
3
0
0
0
0
0
0
TAA0MD2 TAA0MD1 TAA0MD0
TAA1MD2 TAA1MD1 TAA1MD0
TAA2MD2 TAA2MD1 TAA2MD0
TAA3MD2 TAA3MD1 TAA3MD0
TAA4MD2 TAA4MD1 TAA4MD0
TAA5MD2 TAA5MD1 TAA5MD0
2
1
0
Page 216 of 1408
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