UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 256
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3768GF-GAT-AX
Manufacturer Part Number
UPD70F3768GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3768GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3768GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
bit counter is cleared from FFFFH to 0000H, starts counting at the same time, and outputs a PWM waveform from the
TOAAn1 pin. If the trigger is generated again while the counter is operating, the counter is cleared to 0000H and restarted.
(The output of the TOAAn0 pin is inverted. The TOAAn1 pin outputs a high level regardless of the status (high/low) when a
trigger occurs.)
value matches the value of the CCR0 buffer register, and the 16-bit counter is cleared to 0000H at the same time. The
compare match interrupt request signal INTTAAnCC1 is generated when the count value of the 16-bit counter matches the
value of the CCR1 buffer register.
counter matches the value of the CCRm buffer register and the 16-bit counter is cleared to 0000H.
as the trigger.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
16-bit timer/event counter AA waits for a trigger when the TAAnCE bit is set to 1. When the trigger is generated, the 16-
The active level width, cycle, and duty factor of the PWM waveform can be calculated as follows.
The compare match request signal INTTAAnCC0 is generated the next time the 16-bit counter counts after its count
The value set to the TAAnCCRm register is transferred to the CCRm buffer register when the count value of the 16-bit
The valid edge of an external trigger input signal, or setting the software trigger (TAAnCTL1.TAAnEST bit) to 1 is used
Remark
External trigger input
(only when software
INTTAAnCC0 signal
INTTAAnCC1 signal
TAAnCCR0 register
TAAnCCR1 register
TOAAn0 pin output
TOAAn1 pin output
Active level width = (Set value of TAAnCCR1 register) × Count clock cycle
Cycle = (Set value of TAAnCCR0 register + 1) × Count clock cycle
Duty factor = (Set value of TAAnCCR1 register)/(Set value of TAAnCCR0 register + 1)
(TIAAn0 pin input)
trigger is used)
16-bit counter
TAAnCE bit
n = 0 to 3, 5
m = 0, 1
FFFFH
0000H
Figure 7-22. Basic Timing in External Trigger Pulse Output Mode
trigger
Wait
for
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)
D
D
0
1
D
1
D
0
Active level
width (D
Cycle (D
D
1
1
)
D
0
0
+ 1)
Page 256 of 1408
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