UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 338

• Manufacturer Part Number: UPD70F3768GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-U 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3768GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(6) TABn I/O control register 4 (TABnIOC4)
The TABnIOC4 register is an 8-bit register that controls the timer output.
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H. This register is not reset by stopping the timer operation (TABnCTL0.TABnCE = 0).
Cautions 1. Accessing the TABnIOC4 register is prohibited in the following statuses. For details, see 3.4.8
TABnIOC4
(n = 0, 1)
2. The TABnIOC4 register can be set only in the interval timer mode and free-running timer
After reset: 00H
(2) Accessing specific on-chip peripheral I/O registers.
• When the CPU operates on the subclock and the main clock oscillation is stopped
• When the CPU operates on the internal oscillation clock
mode. Be sure to set the TABnIOC4 register to 00H in all other modes (for details of the mode
setting, see 8.4 (2) TABn control register 1 (TABnCTL1)). Even in free-running timer mode, if
the TABnCCR0 to TABnCCR3 registers are set to the capture function, the setting of the
TABnIOC4 register becomes invalid.
TABnOS3
TABnOSm
7
0
0
1
1
TABnORm
TABnOR3 TABnOS2 TABnOR2 TABnOS1 TABnOR1 TABnOS0 TABnOR0
R/W
0
1
0
1
6
Address:
No request. Normal toggle operation.
Reset request
Fix to inactive level upon next match between value of 16-bit
counter and value of TAAnCCRm register.
Set request
Fix to active level upon next match between value of 16-bit
counter and value of TAAnCCRm register.
Keep request
Keep the current output level.
5
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
Toggle control of TOABnm pin (m = 0 to 3)
TAB0IOC4 FFFFF550H, TAB1IOC4 FFFFF570H
4
3
2
1
0
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