UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 350
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3768GF-GAT-AX
Manufacturer Part Number
UPD70F3768GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3768GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3768GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 350 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
8.5.1
TABnCTL0.TABnCE bit is set to 1. A square wave whose half cycle is equal to the interval can be output from the TOABn0
pin.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
In the interval timer mode, an interrupt request signal (INTTABnCC0) is generated at the specified interval if the
Usually, the TABnCCR1 to TABnCCR3 registers are not used in the interval timer mode.
Interval timer mode (TABnMD2 to TABnMD0 bits = 000)
INTTABnCC0 signal
Remark
TABnCCR0 register
Remark
TOABn0 pin output
Count clock
selection
16-bit counter
TABnCE bit
n = 0, 1
n = 0, 1
FFFFH
0000H
TABnCE bit
Figure 8-3. Basic Timing of Operation in Interval Timer Mode
Figure 8-2. Configuration of Interval Timer
Interval (D
D
0
0
+ 1) Interval (D
CCR0 buffer register
TABnCCR0 register
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
16-bit counter
Clear
Match signal
D
0
0
+ 1) Interval (D
D
0
D
0
0
controller
+ 1) Interval (D
Output
INTTABnCC0 signal
D
0
0
+ 1)
TOABn0 pin
Page 350 of 1408
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