UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 931
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UPD70F3768GF-GAT-AX
Manufacturer Part Number
UPD70F3768GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3768GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3768GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
Cautions 1. If DMA is enabled while data is being written to the UF0BI2 register in the PIO mode, a DMA
Bit position
1
2. If 64-byte data is written in the DMA transfer mode, the DMA request signal becomes
3. If the TC signal is received in the DMA transfer mode, the DMA request signal becomes
request is immediately issued.
inactive. If the BKI2NK bit is then set to 1, data is transmitted in synchronization with an IN
token. The DMA request signal becomes active again as long as the DMA request is not
masked as soon as the FIFO is toggled. If the BKI2NK bit is not set, data is not transmitted
even if an IN token has been received. In this case, set the BKI2DED bit of the UF0DEND
register to 1.
inactive. At the same time, the DMA request is masked. If the BKI2NK bit is not set to 1,
data is not transmitted even if an IN token is received. When the BKI2DED bit of the
UF0DEND register is set to 1 by FW, data is transmitted in synchronization with the IN
token. To execute DMA transfer again, unmask the DMA request.
BKI2NK
Bit name
This bit controls NAK to Endpoint3 (bulk 2 transfer (IN)).
This bit is cleared to 0 only when the FIFO connected to the SIE side of the UF0BI2
register (64-byte FIFO of bank configuration) cannot receive data. It is set to 1 when a
toggle operation is performed (the data of the UF0BI2 register is retained until
transmission has been correctly completed). The bank is changed (toggle operation)
when the following conditions are satisfied.
This bit is automatically set to 1 and data transmission is started when the FIFO on the
CPU side becomes full and a FIFO toggle operation is performed as a result of writing
data to the FIFO. However, if the FIFO on the CPU side becomes full as a result of writing
data to it by DMA while the BKI2T bit of the UF0DEND register is cleared to 0, the toggle
operation is not performed because the condition of the toggle operation is not satisfied
until the BKI2DED bit of the UF0DEND register is set to 1. To send a short packet that
does not make the FIFO on the CPU side full, set the BKI2DED bit to 1 after completing
writing data. When the BKI2DED bit is set to 1, a toggle operation is performed and at the
same time, this bit is automatically set to 1. This bit is also cleared to 0 as soon as the
UF0BI2 register has been cleared.
1: Do not transmit NAK.
0: Transmit NAK (default value).
• Data is correctly written to the FIFO connected to the CPU bus side (writing has
• The value of the FIFO counter connected to the SIE side is 0.
been completed and the FIFO is full or the UF0DEND register is set).
CHAPTER 20 USB FUNCTION CONTROLLER (USBF)
Function
Page 931 of 1408
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