UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 806
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3768GF-GAT-AX
Manufacturer Part Number
UPD70F3768GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3768GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3768GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
SIFn pin capture
INTCFnR signal
INTCFnT signal
(2) Operation timing
CFnTSF bit
SCKFn pin
SOFn pin
SIFn pin
(1) Write 07H to the CFnCTL1 register, and select communication type 1, communication clock (f
(2) Write 00H to the CFnCTL2 register, and set the transfer data length to 8 bits.
(3) Write E3H to the CFnCTL0 register, and select the transmission/reception mode, MSB first, and
(4) The CFnSTR.CFnTSF bit is set to 1 by writing the transmit data to the CFnTX register, and the device
(5) When a serial clock is input, output the transmit data to the SOFn pin in synchronization with the serial
(6) When transfer of the transmit data from the CFnTX register to the shift register is completed and
(7) To continue transmission, write the transmit data to the CFnTX register again after the INTCFnT signal
(8) When reception of the transfer data length set with the CFnCTL2 register is completed, the reception
(9) When a serial clock is input continuously, continuous transmission/reception is started.
(10) Read the CFnRX register.
(11) When transfer of the transmit data from the CFnTX register to the shift register is completed and
Remark
timing
external clock (SCKFn), and slave mode.
continuous transfer mode at the same time as enabling the operation of the communication clock
(f
waits for a serial clock input.
clock, and capture the receive data of the SIFn pin.
writing to the CFnTX register is enabled, the transmission enable interrupt request signal (INTCFnT) is
generated.
is generated.
completion interrupt request signal (INTCFnR) is generated, and reading of the CFnRX register is
enabled.
writing to the CFnTX register is enabled, the INTCFnT signal is generated.
transmission/reception with the current transmission/reception, do not write to the CFnTX register.
CCLK
(1)
(2)
(3)
).
n = 0 to 4
(4)
(5)
Bit 7
Bit 7
(6)
Bit 6
Bit 6
Bit 5
Bit 5
(7)
Bit 4
Bit 4
Bit 3 Bit 2
Bit 3 Bit 2
CHAPTER 18 3-WIRE VARIABLE-LENGTH SERIAL I/O (CSIF)
Bit 1
Bit 1
(8) (9) (10)
Bit 0
Bit 0
Bit 7
Bit 7
Bit 6
Bit 6
Bit 5
Bit 5
(11)
Bit 4
Bit 4
Bit 3 Bit 2
Bit 3 Bit 2
Bit 1
Bit 1
(12)
Bit 0
Bit 0
To end continuous
(13) (15)
Page 806 of 1408
CCLK
) =
(1/2)
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