UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 383

• Manufacturer Part Number: UPD70F3768GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-U 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3768GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
from FFFFH to 0000H, starts counting, and outputs a one-shot pulse from the TOABnk pin. After the one-shot pulse is
output, the 16-bit counter is set to FFFFH, stops counting, and waits for a trigger. If a trigger is generated again while the
one-shot pulse is being output, it is ignored.
count value matches the value of the CCR0 buffer register. The compare match interrupt request signal (INTTABnCCk) is
generated when the count value of the 16-bit counter matches the value of the CCRk buffer register.
trigger.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
TABnCTL1
TABnCTL0
When the TABnCE bit is set to 1, TABn waits for a trigger. When the trigger is generated, the 16-bit counter is cleared
The output delay period and active level width of the one-shot pulse can be calculated as follows.
The compare match interrupt request signal INTTABnCC0 is generated when the 16-bit counter counts up after its
The valid edge of the external trigger input or setting the software trigger (TABnCTL1.TABnEST bit) to 1 is used as the
Remark
Output delay period = (Set value of TABnCCRk register) × Count clock cycle
Active level width = (Set value of TABnCCR0 register − Set value of TABnCCRk register + 1) × Count clock cycle
(a) TABn control register 0 (TABnCTL0)
(b) TABn control register 1 (TABnCTL1)
Note The setting is invalid when the TABnCTL1.TABnEEE bit = 1.
Remark
TABnSYE
k = 1 to 3,
n = 0, 1
TABnCE
0/1
0
Figure 8-22. Register Setting for Operation in One-Shot Pulse Output Mode (1/3)
n = 0, 1
TABnEST
0/1
0
TABnEEE
0/1
0
0
0
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
0
0
TABnMD2 TABnMD1 TABnMD0
TABnCKS2 TABnCKS1 TABnCKS0
0/1
0
0/1
1
0/1
1
0, 1, 1:
One-shot pulse output mode
Generate software trigger
when 1 is written
0: Operate on count clock
1: Count by external event
Select count clock
0: Stop counting
1: Enable counting
selected by TABnCKS0 to
TABnCKS2 bits
count input signal
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Note