UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 456
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3768GF-GAT-AX
Manufacturer Part Number
UPD70F3768GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3768GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3768GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 456 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(14) Noise elimination control register (TTNFC)
Digital noise elimination can be selected for the TIT00, TIT01, TENC01, TECR0, and EVTT00 pins. The noise
elimination settings are performed using the TTNFC register.
When digital noise elimination is selected, the sampling clock for digital sampling can be selected from among f
f
This register can be read or written in 8-bit units.
Reset sets this register to 00H.
Caution Time equal to the sampling clock × 3 clocks is required until the digital noise eliminator is
XX
/4, f
XX
TTNFC
/8, f
After reset: 00H
initialized after the sampling clock has been changed. If the valid edge of the TIT00, TIT01,
TENC01, TECR0, and EVTT pins is input after the sampling clock has been changed and before
the time of the sampling clock × 3 clocks passes, therefore, an interrupt request signal may be
generated. Therefore, when using the external trigger function, the external event function, the
capture trigger function, and the encoder function of TMT, enable TMT operation after the
sampling clock × 3 clocks have elapsed.
XX
/16, f
TTNFEN
TTNFEN
TTNFC2
Remarks 1. Since sampling is performed three times, the noise width for reliably
XX
/32, and f
0
1
0
0
0
0
1
1
Other than above
Digital noise elimination not executed
Digital noise elimination executed
TTNFC1
R/W
2. In the case of noise with a width smaller than 2 sampling clocks, an
XX
0
0
0
1
1
0
0
eliminating noise is 2 sampling clocks.
interrupt request signal is generated if noise synchronized with the
sampling clock is input.
/64. Sampling is performed 3 times.
Address: FFFFF726H
TTNFC0
0
1
0
1
0
1
0
Settings of digital noise elimination
f
f
f
f
f
f
Setting prohibited
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
XX
XX
XX
XX
XX
XX
/4
/8
/16
/32
/64
0
0
Digital sampling clock
TTNFC2 TTNFC1 TTNFC0
Page 456 of 1408
XX
,
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