UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 359
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UPD70F3768GF-GAT-AX
Manufacturer Part Number
UPD70F3768GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3768GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3768GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 359 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
8.5.2
TABnCTL0.TABnCE bit is set to 1, and an interrupt request signal (INTTABnCC0) is generated each time the specified
number of edges have been counted. The TOABn0 pin cannot be used.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
In the external event count mode, the valid edge of the external event count input is counted when the
Usually, the TABnCCR1 to TABnCCR3 registers are not used in the external event count mode.
TIAB00 pin
(external event
count input)
Note TAB1: EVTAB1 pin
INTTABnCC0 signal
Note TAB1: EVTAB1 pin
Remark
TABnCCR0 register
External event count mode (TABnMD2 to TABnMD0 bits = 001)
16-bit counter
TABnCE bit
Note
This figure shows the basic timing when the rising edge is specified as the valid edge of the external
event count input.
FFFFH
0000H
detector
External
event
count
interval
(D
Edge
Figure 8-10. Basic Timing in External Event Count Mode
0
Figure 8-9. Configuration in External Event Count Mode
D
+ 1)
0
TABnCE bit
External
event
count
interval
(D
D
0
D
+ 1)
0
0
External
event
count
interval
(D
0
D
CHAPTER 8 16-BIT TIMER/EVENT COUNTER AB (TAB)
+ 1)
0
CCR0 buffer register
TABnCCR0 register
16-bit counter
(TIAB00 pin input)
INTTABnCC0 signal
TABnCCR0 register
Clear
External event
16-bit counter
Match signal
count input
Note
D
0
− 1
D
INTTABnCC0 signal
D
0
0
Page 359 of 1408
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