UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 1142

• Manufacturer Part Number: UPD70F3768GF-GAT-AX
• Description: MCU 32BIT V850ES/JX3-U 128-LQFP
• Manufacturer: Renesas Electronics America
• Series: V850ES/Jx3-Ur

Specifications of UPD70F3768GF-GAT-AX

• Core Processor: RISC
• Core Size: 32-Bit
• Speed: 48MHz
• Connectivity: CSI, EBI/EMI, I²C, UART/USART, USB
• Peripherals: DMA, LVD, PWM, WDT
• Number Of I /o: 96
• Program Memory Size: 384KB (384K x 8)
• Program Memory Type: FLASH
• Ram Size: 48K x 8
• Voltage - Supply (vcc/vdd): 2.85 V ~ 3.6 V
• Data Converters: A/D 12x10b; D/A 2x8b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: *
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
4
3
2
Bit position R/W
R
W
R
W
R
W
PRS
SPR
POCI
CPS
PSS
SPS
Bit name
Port Reset Status
Indicates that reset is being issued for a downstream port.
This bit is cleared (0) together with setting of the PRSC bit when port reset of 10 ms
ends.
This bit cannot be set when the CSC bit has been cleared (0) (no device connected).
Set Port Reset
Issues port reset for a downstream port.
Writing “1” to this bit starts port reset of 10 ms. When “1” is written to this bit while
the CCS bit is cleared (0), the CSC bit is set and it is reported to the host controller
driver that an attempt was made to reset the disconnected port. Writing “0” to this bit
is ignored.
Port Overcurrent Indicator
Indicates the overcurrent status at a downstream port.
Clear Port Suspend
Ends Suspend mode and starts the resume sequence.
Writing “1” to this bit starts the resume sequence. Writing “0” to this bit is ignored.
Resume starts only when the PSS bit has been set.
Port Suspend Status
Indicates that ports are in the Suspend state or the resume sequence is being
executed.
This bit cannot be set when the CCS bit has been cleared to 0 (no device
connected).
Writing to the SPS bit sets ports to the Suspend state. This bit is cleared (0) when
resume ends, port reset ends, or when the state shifts to USB RESUME.
Set Port Suspend
Shifts the port status to the Suspend state.
When “1” is written to this bit, ports enter the Suspend state. Writing “0” to this bit is
ignored.
If this bit is written when the CCS bit has been cleared to 0, the CSC bit is set and it
is reported to the host controller driver that an attempt was made to suspend the
disconnected port.
1: The port is being reset.
0: The port is not being reset.
1: The port is in the overcurrent state.
0: The port is in the normal state.
1: Ports are in the Suspend state.
0: Ports are in the normal transfer state.
CHAPTER 21 USB HOST CONTROLLER (USBH)
Function
Page 1142 of 1408
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