UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 739
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UPD70F3768GF-GAT-AX
Manufacturer Part Number
UPD70F3768GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3768GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3768GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
17.5 Interrupt Request Signals
transmission enable interrupt request signal.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
The following two interrupt request signals are generated from UARTCn.
• Reception completion interrupt request signal (INTUCnR)
• Transmission enable interrupt request signal (INTUCnT)
The default priority for these two interrupt request signals is reception completion interrupt request signal then
(1) Reception completion interrupt request signal (INTUCnR)
(2) Transmission enable interrupt request signal (INTUCnT)
A reception completion interrupt request signal is output when data is shifted into the receive shift register and
transferred to the UCnRX register in the reception enabled status.
A reception completion interrupt request signal is also output when a reception error occurs. Therefore, when a
reception completion interrupt request signal is acknowledged and the data is read, read the UCnSTR register and
check that the reception result is not an error.
No reception completion interrupt request signal is generated in the reception disabled status.
If transmit data is transferred from the UCnTX register to the UARTCn transmit shift register with transmission
enabled, the transmission enable interrupt request signal is generated.
Table 17-3. Interrupts and Their Default Priorities
Reception complete
Transmission enable
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
Interrupt
Priority
High
Low
Page 739 of 1408
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