UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 1074
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UPD70F3768GF-GAT-AX
Manufacturer Part Number
UPD70F3768GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3768GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3768GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
Remarks 1. The above flowchart shows the case where the transfer by DMA channel 2 is from Endpoint2 to
2. ♦: Processing by hardware
internal data RAM, and the transfer by DMA channel 3 is from internal data RAM to Endpoint1.
Figure 20-32. DMA Processing by Bulk Transfer (OUT) (1/3)
(Endpoint2 (UF0BO1)) DBC2
endpoint using UFDRQEN
Setting address (DDA3) of
USB setting (DMA related)
• DMAEDM = 0 (UF0IM0)*
• BKI1NM = 0 (UF0IM2)
• BKI1DTM = 0 (UF0IM2)
• BKO1NLM = 0 (UF0IM3)
• BKO1DTM = 0 (UF0IM3)
request signal as the DMA
request signal as the DMA
Transfer of DMA channel 3
Specifying DMA channel
Setting address (DDA2) of
Setting address (DSA2) of
Setting address (DSA3) of
and transfer destination
DADC2 register = 0080H
DADC3 register = 0020H
UF0IDR register = 02H
DBC3 register = 003FH*
DQBO1MS = 1(UF0IDR)
(setting demand mode)
DQBI1MS = 1 (UF0IDR)
Setting DMA channel 2
Setting DMA channel 3
Setting DMA channel 2
The use of an interrupt
start trigger is disabled.
Setting DMA channel 3
The use of an interrupt
start trigger is disabled.
DTFR3 register = 00H
DTFR2 register = 00H
(Endpoint1 (UF0BI1))
UF0E2DC1 = 0001H
UF0E1DC1 = 0001H
transfer destination
(internal data RAM)
transfer destination
(internal data RAM)
E22 = 1 (DCHC2)
E33 = 1 (DCHC3)
transfer source
transfer source
is completed?
register
START
(1)
Yes
CHAPTER 20 USB FUNCTION CONTROLLER (USBF)
*: When transferring less than 64 bytes,
*: Release the mask setting of the
change the set value.
necessary interrupts
No
(2)
(4)
(3)
Page 1074 of 1408
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