UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 756
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3768GF-GAT-AX
Manufacturer Part Number
UPD70F3768GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3768GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3768GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 756 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(3) UARTCn control register 2 (UCnCTL2)
The UCnCTL2 register is an 8-bit register that selects the baud rate (serial transfer speed) clock of UARTCn.
This register can be read or written in 8-bit units.
Reset sets this register to FFH.
Caution Clear the UCnCTL0.UCnPWR bit to 0 or clear the UCnTXE and UCnRXE bits to 00 before rewriting
(n = 0 to 4)
UCnCTL2
the UCnCTL2 register.
After reset FFH
Remark f
UCnBRS7
BRS7
UCn
0
0
0
0
1
1
1
1
:
7
BRS6
UCn
UCnBRS6 UCnBRS5UCnBRS4 UCnBRS3UCnBRS2 UCnBRS1 UCnBRS0
R/W
0
0
0
0
1
1
1
1
UCLK
:
6
: Clock frequency selected by the UCnCTL1.UCnCKS3 to
CHAPTER 17 ASYNCHRONOUS SERIAL INTERFACE C (UARTC)
BRS5
UCn
UCnCTL1.UCnCKS0 bits
Address: UC0CTL2 FFFFFA02H, UC1CTL2 FFFFFA12H,
0
0
0
0
1
1
1
1
:
BRS4
5
UCn
0
0
0
0
1
1
1
1
:
UC2CTL2 FFFFFA22H, UC3CTL2 FFFFFA32H,
UC4CTL2 FFFFFA42H
BRS3
UCn
0
0
0
0
1
1
1
1
4
:
BRS2
UCn
0
1
1
1
1
1
1
1
:
3
BRS1
UCn
×
0
0
1
0
0
1
1
:
2
BRS0
UCn
×
0
1
0
0
1
0
1
:
Default
252
253
254
255
1
(k)
×
4
5
6
:
prohibited
f
f
f
f
UCLK
UCLK
UCLK
UCLK
Serial
f
f
f
Setting
clock
UCLK
UCLK
UCLK
0
:
/252
/253
/254
/255
/4
/5
/6
Page 756 of 1408
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