UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 488
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UPD70F3768GF-GAT-AX
Manufacturer Part Number
UPD70F3768GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3768GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3768GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 488 of 1411
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V850ES/JG3-U, V850ES/JH3-U
9.6.3
is set to 1. When the valid edge of an external trigger input (EVTT0) is detected, 16-bit timer/event counter T starts
counting, and outputs a PWM waveform from the TOT01 pin.
trigger, a square wave that has the set value of the TT0CCR0 register + 1 as half its cycle can also be output from the
TOT00 pin.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
In the external trigger pulse output mode, 16-bit timer/event counter T waits for a trigger when the TT0CTL0.TT0CE bit
Pulses can also be output by generating a software trigger instead of using the external trigger. When using a software
external event
EVTT0 pin
trigger input/
count input)
(external
External trigger pulse output mode (TT0MD3 to TT0MD0 bits = 0010)
Note 1
Notes 1. Since the external trigger input pin and external event count input pin are the same alternate-
Internal count clock
2. Edge detector for external trigger input.
3. Edge detector for external event count input.
function pin, the external event count input function cannot be used.
Set by the TT0IOC2.TT0ETS1 and TT0IOC2.TT0ETS0 bits.
Set by the TT0IOC2.TT0EES1 and TT0IOC2.TT0EES0 bits.
detector
Figure 9-21. Configuration in External Trigger Pulse Output Mode
Edge
Note 3
Software trigger
selection
generation
Count
clock
detector
Edge
TT0CE bit
Note 2
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
control
Count
start
CCR1 buffer register
CCR0 buffer register
TT0CCR1 register
TT0CCR0 register
16-bit counter
Match signal
Match signal
Clear
Transfer
Transfer
S
R
controller
controller
Output
(RS-FF)
Output
INTTT0CC1 signal
INTTT0CC0 signal
Page 488 of 1408
TOT01 pin
TOT00 pin
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