UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 297
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3768GF-GAT-AX
Manufacturer Part Number
UPD70F3768GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3768GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3768GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 297 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(d) Processing of overflow if capture trigger interval is long
If the pulse width is greater than one cycle of the 16-bit counter, care must be exercised because an overflow
may occur more than once from the first capture trigger to the next. First, an example of incorrect processing is
shown below.
The following problem may occur when a long pulse width is measured in the free-running timer mode.
<1> Read the TAAnCCRm register (setting of the default value of the TIAAnm pin input).
<2> An overflow occurs. Nothing is done by software.
<3> An overflow occurs a second time. Nothing is done by software.
<4> Read the TAAnCCRm register.
If an overflow occurs twice or more when the capture trigger interval is long, the correct pulse width may not be
obtained.
If the capture trigger interval is long, slow the count clock to lengthen one cycle of the 16-bit counter, or use
software. An example of how to use software is shown next.
Remark
TAAnCCRm register
Read the overflow flag. If the overflow flag is 1, clear it to 0.
Because the overflow flag is 1, the pulse width can be calculated by (10000H + D
(incorrect).
Actually, the pulse width must be (20000H + D
INTTAAnOV signal
TIAAnm pin input
16-bit counter
TAAnOVF bit
m = 0, 1
n = 0 to 3, 5
Example of incorrect processing when capture trigger interval is long
TAAnCE bit
FFFFH
0000H
CHAPTER 7 16-BIT TIMER/EVENT COUNTER AA (TAA)
D
m0
<1> <2>
m1
− D
m0
1 cycle of 16-bit counter
) because an overflow occurs twice.
Pulse width
D
m0
<3> <4>
D
m1
D
m1
Page 297 of 1408
m1
− D
m0
)
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