UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 1221
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UPD70F3768GF-GAT-AX
Manufacturer Part Number
UPD70F3768GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3768GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3768GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
25.2 Registers
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(1) Power save control register (PSC)
The PSC register is an 8-bit register that controls the standby function. The STP bit of this register is used to
specify the Standby mode. This register is a special register that can be written only by the special sequence
combinations (see 3.4.7 Special registers).
This register can be read or written in 8-bit or 1-bit units.
Reset sets this register to 00H.
Note Standby mode set by STP bit: IDLE1, IDLE2, STOP, or sub-IDLE mode
Cautions 1. Before setting the IDLE1, IDLE2, STOP, or sub-IDLE mode, set the PSMR.PSM1
After reset: 00H
PSC
NMI1M
NMI0M
INTM
2. Settings of the NMI1M, NMI0M, and INTM bits are invalid when HALT mode is
3. If the NMI1M, NMI0M, or INTM bit is set to 1 at the same time the STP bit is set
STP
0
1
0
1
0
1
0
1
0
and PSMR.PSM0 bits and then set the STP bit.
released.
to 1, the setting of NMI1M, NMI0M, or INTM bit becomes invalid. If there is an
unmasked
IDLE1/IDLE2/STOP mode is set, set the bit corresponding to the interrupt
request signal (NMI1M, NMI0M, or INTM) to 1, and then set the STP bit to 1.
Releasing standby mode by INTWDT2 signal enabled
Releasing standby mode by INTWDT2 signal disabled
Releasing standby mode by NMI pin input enabled
Releasing standby mode by NMI pin input disabled
Releasing standby mode by maskable interrupt request signals enabled
Releasing standby mode by maskable interrupt request signals disabled
Normal mode
Standby mode
NMI1M
R/W
Control of releasing standby mode by maskable interrupt request signals
< >
Control of releasing standby mode by INTWDT2 signal
interrupt
Address: FFFFF1FEH
Control of releasing standby mode by NMI pin input
NMI0M
< >
INTM
request
< >
Standby mode
signal
0
Note
setting
being
CHAPTER 25 STANDBY FUNCTION
0
held
STP
< >
pending
0
Page 1221 of 1408
when
the
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