UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 672
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UPD70F3768GF-GAT-AX
Manufacturer Part Number
UPD70F3768GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3768GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
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Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3768GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
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V850ES/JG3-U, V850ES/JH3-U
13.4 Operation
operation mode and the interval time to the WDTM2 register using an 8-bit memory manipulation instruction. After this,
the operation of watchdog timer 2 cannot be stopped.
the count operation has started, write ACH to WDTE within the loop detection time interval.
maskable interrupt request signal (INTWDT2) is generated, depending on the set values of the WDTM2.WDM21 and
WDTM2.WDM20 bits.
reset or standby is released, no internal reset will occur and the CPU clock will switch to the internal oscillation clock.
INTWDT2 signal.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
(2) Watchdog timer enable register (WDTE)
Cautions 1. When a value other than “ACH” is written to the WDTE register, an overflow signal is
Watchdog timer 2 automatically starts in the reset mode following reset release.
The WDTM2 register can be written to only once following reset using byte access. To use watchdog timer 2, write the
The WDTM2.WDCS24 to WDTM2.WDCS20 bits are used to select the watchdog timer 2 loop detection time interval.
Writing ACH to the WDTE register clears the counter of watchdog timer 2 and starts the count operation again. After
If the time interval expires without ACH being written to the WDTE register, a reset signal (WDT2RES) or a non-
When the WDTM2.WDM21 bit is set to 1 (reset mode), if a WDT overflow occurs during oscillation stabilization after a
To not use watchdog timer 2, write 00H to the WDTM2 register.
For the non-maskable interrupt servicing while the non-maskable interrupt request mode is set, see 23.2.2 (2) From
The counter of watchdog timer 2 is cleared and counting restarted by writing “ACH” to the WDTE register.
The WDTE register can be read or written in 8-bit units.
Reset sets this register to 9AH.
2. When a 1-bit memory manipulation instruction is executed for the WDTE register, an
3. To intentionally generate an overflow signal, write a value other than “ACH” to the WDTE
4. The read value of the WDTE register is “9AH” (which differs from written value “ACH”).
WDTE
forcibly output.
overflow signal is forcibly output.
register once, or write data to the WDTM2 register twice.
However, when the operation of watchdog timer 2 is set to be stopped, an overflow signal is
not generated even if data is written to the WDTM2 register twice, or a value other than
“ACH” is written to the WDTE register once.
After reset: 9AH
R/W
Address: FFFFF6D1H
CHAPTER 13 FUNCTIONS OF WATCHDOG TIMER 2
Page 672 of 1408
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