UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 559
![no-image](/images/manufacturer_photos/0/5/560/renesas_electronics_america_sml.jpg)
UPD70F3768GF-GAT-AX
Manufacturer Part Number
UPD70F3768GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3768GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3768GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 559 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
9.6.10 Encoder compare mode (TT0MD3 to TT0MD0 bits = 1000)
compare registers and the input pins for encoder count function (TENC00, TENC01, and TECR0).
the value of the CCRn buffer register (compare match interrupt request signal (INTTT0CCn) is generated), when the edge
of the encoder clear input (TECR0 pin) is detected, and when the clear level condition of TENC00, TENC01, and TECR0
pins is detected.
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
In the encoder compare mode, the encoder is controlled by using both the TT0CCR0 and TT0CCR1 registers as
In this mode, the 16-bit counter can be cleared to 0000H in three ways: when the count value of the counter matches
When the 16-bit counter underflows, the set value of the TT0CCR0 register can be transferred to the counter.
(1) Encoder compare mode operation flow
Encoder compare mode operation processing
(TT0LDE, TT0ECM1, TT0ECM0,
TT0BCL, TT0ECS1, TT0ECS0,
TT0CCR0, TT0CCR1 registers,
(TT0SCE, TT0ZCL, TT0ACL,
(TT0MD3 to TT0MD0 bits),
TT0UDS1, TT0UDS0 bits),
TT0EIS1, TT0EIS0 bits),
Register initial setting
TT0CTL1 register
TT0CTL2 register
TT0IOC3 register
TT0TCW register
Operation end?
TT0CE bit = 1
TT0CE bit = 0
START
END
Yes
Figure 9-55. Encoder Compare Mode Operation Flow
No
: See Figure 9-56 Encoder Compare Mode Operation Processing.
CHAPTER 9 16-BIT TIMER/EVENT COUNTER T (TMT)
Page 559 of 1408
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