UPD70F3768GF-GAT-AX Renesas Electronics America, UPD70F3768GF-GAT-AX Datasheet - Page 844
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UPD70F3768GF-GAT-AX
Manufacturer Part Number
UPD70F3768GF-GAT-AX
Description
MCU 32BIT V850ES/JX3-U 128-LQFP
Manufacturer
Renesas Electronics America
Series
V850ES/Jx3-Ur
Datasheet
1.UPD70F3763GC-UEU-AX.pdf
(1411 pages)
Specifications of UPD70F3768GF-GAT-AX
Core Processor
RISC
Core Size
32-Bit
Speed
48MHz
Connectivity
CSI, EBI/EMI, I²C, UART/USART, USB
Peripherals
DMA, LVD, PWM, WDT
Number Of I /o
96
Program Memory Size
384KB (384K x 8)
Program Memory Type
FLASH
Ram Size
48K x 8
Voltage - Supply (vcc/vdd)
2.85 V ~ 3.6 V
Data Converters
A/D 12x10b; D/A 2x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
*
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
UPD70F3768GF-GAT-AX
Manufacturer:
Renesas Electronics America
Quantity:
10 000
- Current page: 844 of 1411
- Download datasheet (8Mb)
V850ES/JG3-U, V850ES/JH3-U
19.6.6 Wait state
receive data (i.e., is in a wait state).
canceled for both the master and slave devices, the next data transfer can begin (n = 0 to 2).
R01UH0043EJ0300 Rev.3.00
Sep 30, 2010
A wait state is used to notify the communication partner that a device (master or slave) is preparing to transmit or
Setting the SCL0n pin to low level notifies the communication partner of the wait state. When the wait state has been
(a) When master device is in a nine-clock wait state and slave device is in an eight-clock wait state
Transfer lines
Remark
Master
Slave
ACKEn
SDA0n
SCL0n
SCL0n
SCL0n
IICn
IICn
n = 0 to 2
(master: transmission, slave: reception, and IICCn.ACKEn bit = 1)
H
D2
6
6
D1
7
7
Master returns to high
impedance but slave
is in wait state (low level).
Wait after output
of eighth clock.
Figure 19-13. Wait State (1/2)
D0
8
8
Wait state
from slave
9
ACK
9
FFH is written to IICn register or
IICCn.WRELn bit is set to 1.
Wait after output
of ninth clock.
Wait state
from master
IICn data write (cancel wait state)
D7
1
1
D6
2
2
D5
3
3
CHAPTER 19 I
Page 844 of 1408
2
C BUS
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