ATXMEGA32A4-CUR Atmel, ATXMEGA32A4-CUR Datasheet - Page 55

• Manufacturer Part Number: ATXMEGA32A4-CUR
• Description: MCU AVR 32+4 FLASH 49VFBGA
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA32A4-CUR

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 49-VFBGA
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

5.13.5
5.14
5.14.1
8077H–AVR–12/09
Register Description – DMA Channel
TEMPL - DMA Temporary Register Low
CTRLA - DMA Channel Control Register A
• Bit 7:0 - TEMP[7:0]: DMA Temporary Register 0
This register is used when reading 24- and 16-bit registers in the DMA controller. Byte 1 of the
16/24-bit registers is stored here when it is written by the CPU. Byte 1 of the 16/24-bit registers
are stored when byte 0 is read by the CPU. This register can also be read and written from the
user software.
Reading and writing 16- and 24-bit registers requires special attention. Please see detailed
description in the AVR Core manual.
• Bit 7- CHEN: DMA Channel Enable
Setting this bit enables the DMA channel. This bit is automatically cleared when the transaction
is completed. If the DMA channel is enabled and this bit is written to zero, the CHEN bit is not
cleared before the internal transfer buffer is empty and the DMA transfer is aborted.
• Bit 6 - CHRST: DMA Channel Software Reset
Setting this bit enables the channel reset. This bit is automatically cleared when reset is com-
pleted. This bit can only be set when the DMA channel is disabled (CHEN = 0).
• Bit 5 - REPEAT: DMA Channel Repeat Mode
Setting this bit enables the repeat mode. In repeat mode, this bit is cleared by hardware in the
beginning of the last block transfer. The REPCNT register should be configured before setting
the REPEAT bit.
• Bit 4 - TRFREQ: DMA Channel Transfer Request
Setting this bit requests a data transfer on the DMA Channel. This bit is automatically cleared at
the beginning of the data transfer. Writing this bit does not have any effect unless the channel is
enabled.
• Bit 3 - Reserved
This bit is unused and reserved for future use. For compatibility with future devices, always write
this bit to zero when this register is written.
Bit
+0x00
Read/Write
Initial Value
Bit
+0x06
Read/Write
Initial Value
CHEN
R/W
R/W
7
0
7
0
CHRST
R/W
R/W
6
0
6
0
REPEAT
R/W
R/W
5
0
5
0
TRFREQ
R/W
R/W
4
0
4
0
DMTEMP[7:0]
R/W
3
0
R
3
0
-
SINGLE
R/W
R/W
2
0
2
0
R/W
R/W
1
0
1
BURSTLEN[1:0]
0
XMEGA A
R/W
R/W
0
0
0
0
TEMPL
CTRLA
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