ATXMEGA32A4-CUR Atmel, ATXMEGA32A4-CUR Datasheet - Page 219

MCU AVR 32+4 FLASH 49VFBGA

ATXMEGA32A4-CUR

Manufacturer Part Number
ATXMEGA32A4-CUR
Description
MCU AVR 32+4 FLASH 49VFBGA
Manufacturer
Atmel
Series
AVR® XMEGAr
Datasheets

Specifications of ATXMEGA32A4-CUR

Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
49-VFBGA
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA32A4-CUR
Manufacturer:
Atmel
Quantity:
10 000
19.9.3
8077H–AVR–12/09
CTRLC - TWI Master Control Register C
• Bits 7:3 - Reserved
These bits are unused and reserved for future use. For compatibility with future devices, always
write these bits to zero when this register is written.
• Bit 2 - ACKACT: Acknowledge Action
The Acknowledge Action (ACKACT) bit defines the master's acknowledge behavior in Master
Read mode. The Acknowledge Action is executed when a command is written to the CMD bits. If
SMEN in Control Register B is set, the Acknowledge Action is performed when the DATA regis-
ter is read.
Table 19-3
Table 19-3.
• Bit 1:0 - CMD[1:0]: Command
Writing the Command (CMD) bits triggers a master operation as defined by
CMD bits are strobe bits, and always read as zero. The Acknowledge Action is only valid in Mas-
ter Read mode (R). In Master Write mode (W), a command will only result in a Repeated START
or STOP condition. The ACKACT bit and the CMD bits can be written at the same time, and then
the Acknowledge Action will be updated before the command is triggered.
Table 19-4.
Writing a command to the CMD bits will clear the master interrupt flags and the CLKHOLD flag.
Bit
+0x02
Read/Write
Initial Value
CMD[1:0]
00
01
10
11
ACKACT
lists the acknowledge actions.
0
1
7
R
0
-
ACKACT Bit Description
CMD Bit Description
R
6
0
MODE
-
W
R
X
X
X
Action
Send ACK
Send NACK
R
5
0
-
Operation
Reserved
Execute Acknowledge Action succeeded by repeated START
condition
No operation
Execute Acknowledge Action succeeded by a byte receive
Execute Acknowledge Action succeeded by issuing a STOP
condition
R
4
0
-
R
3
0
-
ACKACT
R/W
2
0
R/W
1
0
CMD[1:0]
XMEGA A
Table
R/W
0
0
19-4. The
CTRLC
219

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