ATXMEGA32A4-CUR Atmel, ATXMEGA32A4-CUR Datasheet - Page 270

• Manufacturer Part Number: ATXMEGA32A4-CUR
• Description: MCU AVR 32+4 FLASH 49VFBGA
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA32A4-CUR

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 49-VFBGA
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

24.5
24.6
24.6.1
24.6.2
8077H–AVR–12/09
EBI Clock
SRAM Configuration
No Multiplexing
Multiplexing address byte 0 and 1
The EBI is clocked from the Peripheral 2x (Clk
frequency, but it can also run at two times the CPU Clock frequency. This can be used to lower
the EBI access time. Refer to
Peripheral 2x Clock and how to configure this.
For use with SRAM the EBI can be configured for various address multiplexing modes by using
external address latches, or with no multiplexing. When a limited number of pins on the device
are is available for the EBI, Address Latch Enable (ALE) signals are used to control external
latches that multiplex address lines from the EBI. The available configurations is shown in
tion 24.6.1 on page 270
the SRAM interface signals.
Table 24-1.
When no multiplexing is used, there is a one-to-one connection between the EBI and the SRAM.
No external address latches are used.
Figure 24-2. Non-multiplexed SRAM connection
When address byte 0 (A[7:0]) and address byte 1 (A[15:8]) are multiplexed, they are output from
the same port, and the ALE1 signal from the device control the address latch.
Signal
CS
WE
RE
ALE[2:0]
A[23:0]
D[7:0]
AD[7:0]
SRAM Interface signals
EBI
Description
Chip Select
Write Enable
Read Enable
Address Latch Enable
Address
Data bus
Combined Address and Data
A[21:16]
through
A[15:8]
D[7:0]
A[7:0]
”System Clock and Clock options” on page 76
Section 24.6.4 on page
2PER
) Clock. This clock can run at the CPU Clock
271.
Table 24-1 on page 270
D[7:0]
A[7:0]
A[15:8]
A[21:16]
SRAM
XMEGA A
for details the
describe
Sec-
270