ATXMEGA32A4-CUR Atmel, ATXMEGA32A4-CUR Datasheet - Page 295

• Manufacturer Part Number: ATXMEGA32A4-CUR
• Description: MCU AVR 32+4 FLASH 49VFBGA
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA32A4-CUR

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 49-VFBGA
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8077H–AVR–12/09
VINP is the single ended or internal input.
The application software selects if an 8- or 12-bit result should be generated. A result with lower
resolution will be available faster. See the
a description on how to calculate the propagation delay.
The result registers are 16-bit. An 8-bit result is always represented right adjusted in the 16-bit
result registers. Right adjusted means that the 8 LSB is found in the low byte. A 12-bit result can
be represented both left- or right adjusted. Left adjusted means that the 8 MSB are found in the
high byte.
When the ADC is in signed mode, the MSB represents the sign bit. In 12-bit right adjusted mode,
the sign bit (bit 11) is padded to bits 12-15 to create a signed 16-bit number directly. In 8-bit
mode, the sign bit (bit 7) is padded to the entire high byte.
Figure 25-9 on page 295
nal input range and the result representation with 12-bit right adjusted mode.
Figure 25-9. Signed differential input (with gain), input range, and result representation
Figure 25-10. Signed single ended and internal input, input range, and result representation
VREF
VREF
-VREF
-VREF
GAIN
GAIN
0 V
0 V
RES
=
VINP - (-ΔV )
--------------------------------- - TOP
VREF
to
⋅
Figure 25-11 on page 296
VINN = GND
VINP
VINN
RES
VINP
”ADC Clock and Conversion Timing” on page 296
-2045
-2046
-2047
-2048
-2045
-2046
-2047
-2048
2047
2046
2045
2047
2046
2045
Dec
Dec
-1
-2
...
-1
-2
...
...
...
3
2
1
0
3
2
1
0
7FD
FFE
Hex
7FE
7FD
FFF
FFE
Hex
7FF
7FE
FFF
7FF
803
802
801
800
shows the different input options, the sig-
803
802
801
800
...
...
...
...
3
2
1
0
3
2
1
0
0111 1111 1111
0111 1111 1110
0111 1111 1101
0000 0000 0011
0000 0000 0010
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
1000 0000 0011
1000 0000 0010
1000 0000 0001
1000 0000 0000
0111 1111 1111
0111 1111 1110
0111 1111 1101
0000 0000 0011
0000 0000 0010
0000 0000 0001
0000 0000 0000
1111 1111 1111
1111 1111 1110
1000 0000 0011
1000 0000 0010
1000 0000 0001
1000 0000 0000
Binary
Binary
...
...
...
...
0000 0111 1111 1111
0000 0111 1111 1110
0000 0111 1111 1101
0000 0000 0000 0011
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
1111 1000 0000 0011
1111 1000 0000 0010
1111 1000 0000 0001
1111 1000 0000 0000
16-bit result register
0000 0111 1111 1111
0000 0111 1111 1110
0000 0111 1111 1101
0000 0000 0000 0011
0000 0000 0000 0010
0000 0000 0000 0001
0000 0000 0000 0000
1111 1111 1111 1111
1111 1111 1111 1110
1111 1000 0000 0011
1111 1000 0000 0010
1111 1000 0000 0001
1111 1000 0000 0000
16-bit result register
XMEGA A
...
...
...
...
295
for