ATXMEGA32A4-CUR Atmel, ATXMEGA32A4-CUR Datasheet - Page 341

MCU AVR 32+4 FLASH 49VFBGA

ATXMEGA32A4-CUR

Manufacturer Part Number
ATXMEGA32A4-CUR
Description
MCU AVR 32+4 FLASH 49VFBGA
Manufacturer
Atmel
Series
AVR® XMEGAr
Datasheets

Specifications of ATXMEGA32A4-CUR

Core Processor
AVR
Core Size
8/16-Bit
Speed
32MHz
Connectivity
I²C, IrDA, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, DMA, POR, PWM, WDT
Number Of I /o
34
Program Memory Size
32KB (16K x 16)
Program Memory Type
FLASH
Eeprom Size
2K x 8
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
1.6 V ~ 3.6 V
Data Converters
A/D 12x12b, D/A 2x12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
49-VFBGA
For Use With
ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATXMEGA32A4-CUR
Manufacturer:
Atmel
Quantity:
10 000
28.4.7
28.5
Figure 28-2. JTAG data register overview
28.5.1
8077H–AVR–12/09
Data registers
PDICOM; 0x7
Bypass register
D
D
D
D
D
D
D
D
D
I/O P O R T S
D
P D I
PDICO is an AVR specific instruction and using the JTAG TAP as an alternative interface
towards the PDI (Programming and Debug Interface).
The active states are:
The supported data registers that can be connected between TDI and TDO are:
The Bypass Register consists of a single Shift Register stage. When the Bypass Register is
selected as path between TDI and TDO, the register is reset to 0 when leaving the Capture-DR
controller state. The Bypass Register can be used to shorten the scan chain on a system when
the other devices are to be tested.
D
• Capture-DR: Loads a logical "0" into the Bypass Register.
• Shift-DR: The Bypass Register cell between TDI and TDO is shifted.
• Capture-DR: Parallel data from the PDI is sampled into the PDICOM data register.
• Shift-DR: The PDICOM data register is shifted by the TCK input.
• Update-DR: Commands or operands are parallel-latched from the PDICOM data register into
• Bypass register (Ref: register A in
• Device Identification register (Ref: registers C in
• Boundary-scan chain (Ref: register D in
• PDICOM data register (Ref: register B in
the PDI.
J T A G
A
B
C
In te rn a l re g is te rs
B
C
Figure 28-2 on page
C
Figure 28-2 on page
Figure 28-2 on page
B
C T R L
T A P
C
Figure 28-2 on page
341).
341).
341)
to a ll T C K
re g is te rs
341).
XMEGA A
T M S
T C K
T D O
T D I
341

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