ATXMEGA32A4-CUR Atmel, ATXMEGA32A4-CUR Datasheet - Page 234

• Manufacturer Part Number: ATXMEGA32A4-CUR
• Description: MCU AVR 32+4 FLASH 49VFBGA
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA32A4-CUR

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 49-VFBGA
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

20.7.4
20.8
20.9
Table 20-5.
8077H–AVR–12/09
Address
+0x00
+0x01
+0x02
+0x03
Offset
0x00
Register Summary
SPI Interrupt vectors
DATA - SPI Data Register
Name
SPI Interrupt vector and its offset word address
INTCTRL
STATUS
CTRL
DATA
SPI_vect
• Bit 6 - WRCOL: Write Collision Flag
The WRCOL bit is set if the DATA register is written during a data transfer. The WRCOL bit is
cleared by first reading the STATUS register with WRCOL set, and then accessing the DATA
register.
• Bit 5:0 - Reserved
These bits are reserved and will always be read as zero. For compatibility with future devices,
always write these bits to zero when this register is written.
The DATA register used for sending and receiving data. Writing to the register initiates the data
transmission, and the byte written to the register will be shifted out on the SPI output line. Read-
ing the register causes the Shift Register Receive buffer to be read, and return the last bytes
successfully received.
Source
CLK2X
Bit 7
Bit
+0x03
Read/Write
Initial Value
IF
-
ENABLE
WRCOL
Bit 6
R/W
-
7
0
Interrupt Description
SPI Interrupt vector
R/W
Bit 5
DORD
6
0
-
-
R/W
MASTER
5
0
Bit 4
-
-
DATA[7:0]
R/W
4
0
Bit 3
DATA[7:0]
-
-
MODE[1:0]
R/W
3
0
Bit 2
-
-
R/W
2
0
Bit 1
-
PRESCALER[1:0]
INTLVL[1:0]
R/W
1
0
XMEGA A
Bit 0
-
R/W
0
0
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