ATXMEGA32A4-CUR Atmel, ATXMEGA32A4-CUR Datasheet - Page 25

• Manufacturer Part Number: ATXMEGA32A4-CUR
• Description: MCU AVR 32+4 FLASH 49VFBGA
• Manufacturer: Atmel
• Series: AVR® XMEGAr

Specifications of ATXMEGA32A4-CUR

• Core Processor: AVR
• Core Size: 8/16-Bit
• Speed: 32MHz
• Connectivity: I²C, IrDA, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, DMA, POR, PWM, WDT
• Number Of I /o: 34
• Program Memory Size: 32KB (16K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 2K x 8
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 1.6 V ~ 3.6 V
• Data Converters: A/D 12x12b, D/A 2x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 49-VFBGA
• For Use With: ATAVRONEKIT - KIT AVR/AVR32 DEBUGGER/PROGRMMRATSTK600 - DEV KIT FOR AVR/AVR32770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPI
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

4.14
4.15
4.15.1
4.15.2
4.15.3
8077H–AVR–12/09
IO Memory Protection
Register Description - NVM Controller
ADDR2 - Non-Volatile Memory Address Register 2
ADDR1 - Non-Volatile Memory Address Register 1
ADDR0 - Non-Volatile Memory Address Register 0
from the application software. As long as JTAG is disabled the I/O pins required for JTAG can be
used as normal I/O pins.
Some features in the device is regarded to be critical for safety in some applications. Due to this,
it is possible to lock the IO register related to the Event System and the Advanced Waveform
Extensions. As long as the lock is enabled, all related IO registers are locked and they can not
be written from the application software. The lock registers themselves are protected by the
Configuration Change Protection mechanism, for details refer to
tion” on page
The ADDR2, ADDR1 and ADDR0 registers represents the 24-bit value ADDR.
• Bit 7:0 - ADDR[23:16]: NVM Address Register Byte 2
This register gives the address extended byte when accessing application and boot section.
• Bit 7:0 - ADDR[15:8]: NVM Address Register Byte 1
This register gives the address high byte when accessing either of the memory locations.
• Bit 7:0 - ADDR[7:0]: NVM Address Register Byte 0
This register gives the address low byte when accessing either of the memory locations.
Bit
+0x02
Read/Write
Initial Value
Bit
+0x01
Read/Write
Initial Value
Bit
+0x00
Read/Write
Initial Value
12.
R/W
R/W
R/W
7
0
7
0
7
0
R/W
R/W
R/W
6
0
6
0
6
0
R/W
R/W
R/W
5
0
5
0
5
0
R/W
R/W
R/W
4
0
4
0
4
0
ADDR[23:16]
ADDR[15:8]
ADDR[7:0]
R/W
R/W
R/W
3
0
3
0
3
0
R/W
R/W
R/W
2
0
2
0
2
0
”Configuration Change Protec-
R/W
R/W
R/W
1
0
1
0
1
0
XMEGA A
R/W
R/W
R/W
0
0
0
0
0
0
ADDR2
ADDR1
ADDR0
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